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CH32V208CBU6 (QFN-48(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32V208CBU6

WCHID: C5713556QFN-48(5x5) · 49 Pins · Pitch 0.35mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32V208CBU6 (QFN-48(5x5))1PC13/TAMPER_2PC14/OSC32IN3PC15/OSC32OU4VSSA5OSC_IN6OSC_OUT7NRST8VDDA9PA0/WKUP/ADC10PA1/ADC111PA2/ADC212PA3/ADC313PA4/ADC414PA5/ADC515PA6/ADC616PA7/ADC717PB0/ADC818PB1/ADC919PB2/BOOT120PB1021PB1122VDD_VIO_123PB1224PB1325PB1449EP48VBAT47VDD_VIO_346VSS_345PB944PB843BOOT042PB7/USB2DP41PB6/USB2DM40PB539PB438PB337PA1536PA14/SWCLK35VSS_234ANT33VINTA32PA13/SWDIO31PA12/USB1DP30PA11/USB1DM29PA1028PA927PA826PB15Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.838.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
12345678910252627282930313233342423222120191817161514131211484746454443424140393837363549E=5.00mm · Pitch e=0.35mmD=5.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.35mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PC13/TAMPER_RTCI/OMultiplexed I/O & Peripheral Pin PC13/TAMPER_RTC (RTC/CLK)
2PC14/OSC32INI/OMultiplexed I/O & Peripheral Pin PC14/OSC32IN (RTC/CLK)
3PC15/OSC32OUTI/OMultiplexed I/O & Peripheral Pin PC15/OSC32OUT (RTC/CLK)
4VSSAGNDGround Reference Pin (VSSA)
5OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
6OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
7NRSTISystem Enable & Hardware Reset (NRST)
8VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
9PA0/WKUP/ADC0I/OMultiplexed I/O & Peripheral Pin PA0/WKUP/ADC0 (ADC)
10PA1/ADC1I/OMultiplexed I/O & Peripheral Pin PA1/ADC1 (ADC)
11PA2/ADC2I/OMultiplexed I/O & Peripheral Pin PA2/ADC2 (ADC)
12PA3/ADC3I/OMultiplexed I/O & Peripheral Pin PA3/ADC3 (ADC)
13PA4/ADC4I/OMultiplexed I/O & Peripheral Pin PA4/ADC4 (ADC)
14PA5/ADC5I/OMultiplexed I/O & Peripheral Pin PA5/ADC5 (ADC)
15PA6/ADC6I/OMultiplexed I/O & Peripheral Pin PA6/ADC6 (ADC)
16PA7/ADC7I/OMultiplexed I/O & Peripheral Pin PA7/ADC7 (ADC)
17PB0/ADC8I/OMultiplexed I/O & Peripheral Pin PB0/ADC8 (ADC)
18PB1/ADC9I/OMultiplexed I/O & Peripheral Pin PB1/ADC9 (ADC)
19PB2/BOOT1I/OMultiplexed I/O & Peripheral Pin PB2/BOOT1 (General)
20PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
21PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
22VDD_VIO_1PowerPower Supply Input (VDD_VIO_1 — 3.3V / 5.0V Standard Logic)
23PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
24PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
25PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
26PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
27PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
28PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
29PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
30PA11/USB1DMI/OMultiplexed I/O & Peripheral Pin PA11/USB1DM (USB)
31PA12/USB1DPI/OMultiplexed I/O & Peripheral Pin PA12/USB1DP (USB)
32PA13/SWDIOI/OMultiplexed I/O & Peripheral Pin PA13/SWDIO (SWD/JTAG)
33VINTAPowerPower Supply Input (VINTA — 3.3V / 5.0V Standard Logic)
34ANTI/OMultiplexed I/O & Peripheral Pin ANT (General)
35VSS_2GNDGround Reference Pin (VSS_2)
36PA14/SWCLKI/OMultiplexed I/O & Peripheral Pin PA14/SWCLK (SWD/JTAG)
37PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
38PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
39PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
40PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
41PB6/USB2DMI/OMultiplexed I/O & Peripheral Pin PB6/USB2DM (USB)
42PB7/USB2DPI/OMultiplexed I/O & Peripheral Pin PB7/USB2DP (USB)
43BOOT0IInput-Only Pin BOOT0 (General)
44PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
45PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
46VSS_3GNDGround Reference Pin (VSS_3)
47VDD_VIO_3PowerPower Supply Input (VDD_VIO_3 — 3.3V / 5.0V Standard Logic)
48VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
49EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 PC13/TAMPER_RTC
I/O
Multiplexed I/O & Peripheral Pin PC13/TAMPER_RTC (RTC/CLK)
Design note: Signal terminal PC13/TAMPER_RTC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13/TAMPER_RTC. Supported peripheral buses: RTC/CLK.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 27 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32V208CBU6 (WCH · QFN-48(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32V208CBU6 (QFN-48(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32V208CBU6 (QFN-48(5x5)) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32V208CBU6 (QFN-48(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32V208CBU6 (QFN-48(5x5)) - 4. Package Dimensions (D×E×A)
QFN-48(5x5) · 5.00×5.00mm · Pitch 0.35mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32V208CBU6 (QFN-48(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32V208CBU6 (QFN-48(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (27 figures · Page 1/3)
Showing 1–12 of 27 uncropped original figures for CH32V208 / CH32V305 / CH32V307
P1 · p01_fig01278×171px
CH32V208CBU6 (QFN-48(5x5)) — Overview
Overview
P2 · p02_fig011853×1606px
CH32V208CBU6 (QFN-48(5x5)) — CH32F20x serial products overview | Low-and-medium-density | general (F203) High-density general (F203) Connectivity | (F205) | Interconnectivity | (F207) | Wireless | (F208) | 32K Flash 64K Flash 128K Flash 256K Flash 128K Flash 256K Flash
CH32F20x serial products overview | Low-and-medium-density | general (F203) High-density general (F203) Connectivity | (F205) | Interconnectivity | (F207) | Wireless | (F208) | 32K Flash 64K Flash 128K Flash 256K Flash 128K Flash 256K Flash
P149 · p149_fig011790×852px
CH32V208CBU6 (QFN-48(5x5)) — 10.3.2.4 External Interrupt Configuration Register2 (AFIO_EXTICR2) Offset address: 0x0C
10.3.2.4 External Interrupt Configuration Register2 (AFIO_EXTICR2) Offset address: 0x0C
P149 · p149_fig021790×978px
CH32V208CBU6 (QFN-48(5x5)) — 10.3.2.5 External Interrupt Configuration Register3 (AFIO_EXTICR3) Offset address: 0x10
10.3.2.5 External Interrupt Configuration Register3 (AFIO_EXTICR3) Offset address: 0x10
P149 · p149_fig031790×465px
CH32V208CBU6 (QFN-48(5x5)) — V2.2 145
V2.2 145
P334 · p334_fig011614×599px
CH32V208CBU6 (QFN-48(5x5)) — Figure 20-15 Audio sampling frequency definition
Figure 20-15 Audio sampling frequency definition
P334 · p334_fig021491×762px
CH32V208CBU6 (QFN-48(5x5)) — Figure 20-16 I2S clock generator structure
Figure 20-16 I2S clock generator structure
P484 · p484_fig011740×728px
CH32V208CBU6 (QFN-48(5x5)) — Figure 27-2 Block diagram of Ethernet Transceiver
Figure 27-2 Block diagram of Ethernet Transceiver
P484 · p484_fig021771×1288px
CH32V208CBU6 (QFN-48(5x5)) — V2.2 480
V2.2 480
P484 · p484_fig02P484
CH32V208CBU6 (QFN-48(5x5)) — Datasheet Page 484 (p484_fig02)
Datasheet Page 484 (p484_fig02)
P492 · p492_fig011589×1146px
CH32V208CBU6 (QFN-48(5x5)) — Figure 27-8 Ethernet peripheral clock tree
Figure 27-8 Ethernet peripheral clock tree
P492 · p492_fig02720×379px
CH32V208CBU6 (QFN-48(5x5)) — NIAC GTXC RGMII_EN }-—» GRXC ETH1G_EN PLL2VCO ETH1G_125M PLL3VCO ETH1G_SRC RGMIII interface
NIAC GTXC RGMII_EN }-—» GRXC ETH1G_EN PLL2VCO ETH1G_125M PLL3VCO ETH1G_SRC RGMIII interface
Page 1 / 3 (27 extracted figures)

Technical Specifications & Part Details (CH32V208CBU6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:CH32V208CBU6 (QFN-48(5x5)) is a 48-pin embedded microcontroller unit (mcu) featuring a 5.00 × 5.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, I2S, ADC, DAC, SDIO, RTC/CLK, SWD/JTAG, USB interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
8MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-48(5x5))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, I2S, ADC, DAC, SDIO, RTC/CLK, SWD/JTAG, USB
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2/BOOT1, BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.35mm
OK
IPC-7525 60% Solder PasteEPAD 3.70×3.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — CH32V208 / CH32V305 / CH32V307 (15)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (QFN-48(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.35mm
Pad Size (W × L)Level B
0.16 × 0.75 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-48(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32V208CBU6 (QFN-48(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32V208CBU6 (QFN-48(5x5))?

Manufactured by WCH, the CH32V208CBU6 is housed in a QFN-48(5x5) package with 49 pins and a 0.35 mm lead pitch. Key pins include: 1 (PC13/TAMPER_RTC: Multiplexed I/O & Peripheral Pin PC13/TAMPER_RTC (RTC/CLK)), 2 (PC14/OSC32IN: Multiplexed I/O & Peripheral Pin PC14/OSC32IN (RTC/CLK)), 3 (PC15/OSC32OUT: Multiplexed I/O & Peripheral Pin PC15/OSC32OUT (RTC/CLK)), 4 (VSSA: Ground Reference Pin (VSSA)), 5 (OSC_IN: Multiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)), 6 (OSC_OUT: Multiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for CH32V208CBU6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32V208CBU6 (QFN-48(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.35 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 3.70 × 3.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32V208CBU6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32V208CBU6 (WCH, QFN-48(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & CH32V208 / CH32V305 / CH32V307 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PC13/TAMPER_RTCDigital_IOSignal terminal PC13/TAMPER_RTC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13/TAMPER_RTC. Supported peripheral buses: RTC/CLK.
2PC14/OSC32INDigital_IOSignal terminal PC14/OSC32IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14/OSC32IN. Supported peripheral buses: RTC/CLK.
3PC15/OSC32OUTDigital_IOSignal terminal PC15/OSC32OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC15/OSC32OUT. Supported peripheral buses: RTC/CLK.
4VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
5OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
6OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
9PA0/WKUP/ADC0AnalogSignal terminal PA0/WKUP/ADC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0/WKUP/ADC0. Supported peripheral buses: ADC.
10PA1/ADC1AnalogSignal terminal PA1/ADC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1/ADC1. Supported peripheral buses: ADC.
11PA2/ADC2AnalogSignal terminal PA2/ADC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2/ADC2. Supported peripheral buses: ADC.
12PA3/ADC3AnalogSignal terminal PA3/ADC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3/ADC3. Supported peripheral buses: ADC.
13PA4/ADC4AnalogSignal terminal PA4/ADC4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4/ADC4. Supported peripheral buses: ADC.
14PA5/ADC5AnalogSignal terminal PA5/ADC5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5/ADC5. Supported peripheral buses: ADC.
15PA6/ADC6AnalogSignal terminal PA6/ADC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6/ADC6. Supported peripheral buses: ADC.
16PA7/ADC7AnalogSignal terminal PA7/ADC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7/ADC7. Supported peripheral buses: ADC.
17PB0/ADC8AnalogSignal terminal PB0/ADC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0/ADC8. Supported peripheral buses: ADC.
18PB1/ADC9AnalogSignal terminal PB1/ADC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1/ADC9. Supported peripheral buses: ADC.
19PB2/BOOT1Digital_IOSignal terminal PB2/BOOT1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2/BOOT1. Supported peripheral buses: General.
20PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
21PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
22VDD_VIO_1Power_InPrimary positive power supply input (VDD_VIO_1) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
23PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
24PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
25PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
26PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
27PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
28PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
29PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
30PA11/USB1DMDigital_IOSignal terminal PA11/USB1DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11/USB1DM. Supported peripheral buses: USB.
31PA12/USB1DPDigital_IOSignal terminal PA12/USB1DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12/USB1DP. Supported peripheral buses: USB.
32PA13/SWDIODigital_IOSignal terminal PA13/SWDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13/SWDIO. Supported peripheral buses: SWD/JTAG.
33VINTAPower_InPrimary positive power supply input (VINTA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
34ANTRF_50OhmSignal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General.
35VSS_2GND0V electrical ground return terminal (VSS_2) for internal core logic, I/O drivers, and analog sub-blocks.
36PA14/SWCLKDigital_IOSignal terminal PA14/SWCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14/SWCLK. Supported peripheral buses: SWD/JTAG.
37PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
38PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
39PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
40PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
41PB6/USB2DMDigital_IOSignal terminal PB6/USB2DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6/USB2DM. Supported peripheral buses: USB.
42PB7/USB2DPDigital_IOSignal terminal PB7/USB2DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7/USB2DP. Supported peripheral buses: USB.
43BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
44PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
45PB9Digital_IOSignal terminal PB9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
46VSS_3GND0V electrical ground return terminal (VSS_3) for internal core logic, I/O drivers, and analog sub-blocks.
47VDD_VIO_3Power_InPrimary positive power supply input (VDD_VIO_3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
48VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
49EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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