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CH32V305FBP6 (TSSOP-20-175mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32V305FBP6

WCHID: C5123443TSSOP-20-175mil · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32V305FBP6 (TSSOP-20-175mil)1RST#2IO23PB10/UART3_T4PB11/UART3_R5PB12/SPI2_NS6IO37NC8IO09PC610PC720OSC_OUT/PD119OSC_IN/PD018VSS/GND17PB7/USB2DP/U16PB6/USB2DM/U15PA14/SWCLK14VDD33/VIO13IO1512PC9/PA8/UART11PC8Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=4.40mm · Pitch e=0.65mmD=6.50mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 4.40mm × 6.50mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RST#I/OMultiplexed I/O & Peripheral Pin RST# (General)
2IO2I/OGeneral Purpose Digital I/O Pin IO2
3PB10/UART3_TX/I2C2_SCLI/OMultiplexed I/O & Peripheral Pin PB10/UART3_TX/I2C2_SCL (UART, I2C)
4PB11/UART3_RX/I2C2_SDAI/OMultiplexed I/O & Peripheral Pin PB11/UART3_RX/I2C2_SDA (UART, I2C)
5PB12/SPI2_NSS/CAN2_RXI/OMultiplexed I/O & Peripheral Pin PB12/SPI2_NSS/CAN2_RX (SPI, CAN)
6IO3I/OGPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)
7NCNCNo Connect (Leave Floating)
8IO0I/OGPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
10PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
11PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
12PC9/PA8/UART1_RXI/OMultiplexed I/O & Peripheral Pin PC9/PA8/UART1_RX (UART)
13IO15I/OGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14VDD33/VIOPowerPower Supply Input (VDD33/VIO — 3.3V / 5.0V Standard Logic)
15PA14/SWCLKI/OMultiplexed I/O & Peripheral Pin PA14/SWCLK (SWD/JTAG)
16PB6/USB2DM/UART1X_TXI/OMultiplexed I/O & Peripheral Pin PB6/USB2DM/UART1X_TX (USB, UART)
17PB7/USB2DP/UART1X_RXI/OMultiplexed I/O & Peripheral Pin PB7/USB2DP/UART1X_RX (USB, UART)
18VSS/GNDGNDGround Reference Pin (VSS/GND)
19OSC_IN/PD0I/OMultiplexed I/O & Peripheral Pin OSC_IN/PD0 (RTC/CLK)
20OSC_OUT/PD1I/OMultiplexed I/O & Peripheral Pin OSC_OUT/PD1 (RTC/CLK)
PIN 1 RST#
I/O
Multiplexed I/O & Peripheral Pin RST# (General)
Design note: Signal terminal RST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST#. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32V305FBP6 (WCH · TSSOP-20-175mil)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32V305FBP6 (TSSOP-20-175mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32V305FBP6 (TSSOP-20-175mil) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32V305FBP6 (TSSOP-20-175mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32V305FBP6 (TSSOP-20-175mil) - 4. Package Dimensions (D×E×A)
TSSOP-20-175mil · 4.40×6.50mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32V305FBP6 (TSSOP-20-175mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32V305FBP6 (TSSOP-20-175mil) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for CH32V208 / CH32V305 / CH32V307
P1 · p01_fig01278×171px
CH32V305FBP6 (TSSOP-20-175mil) — Overview
Overview
P23 · p23_fig011472×899px
CH32V305FBP6 (TSSOP-20-175mil) — CH32V307VCT6 CH32V307WCU6
CH32V307VCT6 CH32V307WCU6
P23 · p23_fig01P23
CH32V305FBP6 (TSSOP-20-175mil) — Datasheet Page 23 (p23_fig01)
Datasheet Page 23 (p23_fig01)
P81 · p81_fig011852×1110px
CH32V305FBP6 (TSSOP-20-175mil) — The above formula is used to determine the maximum external impedance so that the error can be less than 1/4 LSB. Where N=12 (representing 12-bit resolution). | Table 4-42 Maximum RAIN when fADC = 14MHz | TS(cycle) tS (us) Maximum RAIN(kΩ)
The above formula is used to determine the maximum external impedance so that the error can be less than 1/4 LSB. Where N=12 (representing 12-bit resolution). | Table 4-42 Maximum RAIN when fADC = 14MHz | TS(cycle) tS (us) Maximum RAIN(kΩ)
P81 · p81_fig01P81
CH32V305FBP6 (TSSOP-20-175mil) — Datasheet Page 81 (p81_fig01)
Datasheet Page 81 (p81_fig01)
P90 · p90_fig011287×1064px
CH32V305FBP6 (TSSOP-20-175mil) — Figure 5-6 LQFP100 package
Figure 5-6 LQFP100 package
P91 · p91_fig011564×2234px
CH32V305FBP6 (TSSOP-20-175mil) — G = 28 pins K = 32 pins T = 36 pins C = 48 pins R = 64 pins
G = 28 pins K = 32 pins T = 36 pins C = 48 pins R = 64 pins

Technical Specifications & Part Details (CH32V305FBP6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:CH32V305FBP6 (TSSOP-20-175mil) is a 20-pin embedded microcontroller unit (mcu) featuring a 6.50 × 4.40 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, CAN, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
144MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.50 × 4.40 × 1.00 mm (A1=0.10 mm)
Package family: TSSOP (TSSOP-20-175mil)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, CAN, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TSSOP-20-175mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.50 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.45 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TSSOP-20-175mil
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32V305FBP6 (TSSOP-20-175mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32V305FBP6 (TSSOP-20-175mil)?

Manufactured by WCH, the CH32V305FBP6 is housed in a TSSOP-20-175mil package with 20 pins and a 0.65 mm lead pitch. Key pins include: 1 (RST#: Multiplexed I/O & Peripheral Pin RST# (General)), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (PB10/UART3_TX/I2C2_SCL: Multiplexed I/O & Peripheral Pin PB10/UART3_TX/I2C2_SCL (UART, I2C)), 4 (PB11/UART3_RX/I2C2_SDA: Multiplexed I/O & Peripheral Pin PB11/UART3_RX/I2C2_SDA (UART, I2C)), 5 (PB12/SPI2_NSS/CAN2_RX: Multiplexed I/O & Peripheral Pin PB12/SPI2_NSS/CAN2_RX (SPI, CAN)), 6 (IO3: GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)).

What are the IPC-7351B PCB Footprint dimensions for CH32V305FBP6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32V305FBP6 (TSSOP-20-175mil) has a nominal body envelope of 4.40 × 6.50 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32V305FBP6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32V305FBP6 (WCH, TSSOP-20-175mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & CH32V208 / CH32V305 / CH32V307 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RST#Digital_IOSignal terminal RST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST#. Supported peripheral buses: General.
2IO2Digital_IOGeneral Purpose Digital I/O Pin IO2
3PB10/UART3_TX/I2C2_SCLDigital_IOSignal terminal PB10/UART3_TX/I2C2_SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10/UART3_TX/I2C2_SCL. Supported peripheral buses: UART, I2C.
4PB11/UART3_RX/I2C2_SDADigital_IOSignal terminal PB11/UART3_RX/I2C2_SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11/UART3_RX/I2C2_SDA. Supported peripheral buses: UART, I2C.
5PB12/SPI2_NSS/CAN2_RXDigital_IOSignal terminal PB12/SPI2_NSS/CAN2_RX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12/SPI2_NSS/CAN2_RX. Supported peripheral buses: SPI, CAN.
6IO3Digital_IOGPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)
7NCNo_ConnectNo Connect (Leave Floating)
8IO0Digital_IOGPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9PC6Digital_IOSignal terminal PC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
10PC7Digital_IOSignal terminal PC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
11PC8Digital_IOSignal terminal PC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
12PC9/PA8/UART1_RXDigital_IOSignal terminal PC9/PA8/UART1_RX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC9/PA8/UART1_RX. Supported peripheral buses: UART.
13IO15Digital_IOGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14VDD33/VIOPower_InPrimary positive power supply input (VDD33/VIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
15PA14/SWCLKDigital_IOSignal terminal PA14/SWCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14/SWCLK. Supported peripheral buses: SWD/JTAG.
16PB6/USB2DM/UART1X_TXDigital_IOSignal terminal PB6/USB2DM/UART1X_TX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6/USB2DM/UART1X_TX. Supported peripheral buses: USB, UART.
17PB7/USB2DP/UART1X_RXDigital_IOSignal terminal PB7/USB2DP/UART1X_RX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7/USB2DP/UART1X_RX. Supported peripheral buses: USB, UART.
18VSS/GNDGND0V electrical ground return terminal (VSS/GND) for internal core logic, I/O drivers, and analog sub-blocks.
19OSC_IN/PD0Digital_IOSignal terminal OSC_IN/PD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_IN/PD0. Supported peripheral buses: RTC/CLK.
20OSC_OUT/PD1Digital_IOSignal terminal OSC_OUT/PD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_OUT/PD1. Supported peripheral buses: RTC/CLK.
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