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CH32V303VCT6 (LQFP-100(14x14)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32V303VCT6

WCHID: C5357073LQFP-100(14x14) · 100 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32V303VCT6 (LQFP-100(14x14))1PE22PE33PE44PE55PE66VBAT7PC13/TAMPER-8PC14/OSC32IN9PC15/OSC320U10VSS_511VDD_512OSC_IN13OSC_OUT14NRST15PC0/ADC1016PC1/ADC1117PC2/ADC1218PC3/ADC1319VSSA20VREF-21VREF+22VDDA23PA0/WKUP/ADC24PA1/ADC125PA2/ADC226PA3/ADC327VSS_428VDD_429PA4/ADC4/DAC30PA5/ADC5/DAC31PA6/ADC632PA7/ADC733PC4/ADC1434PC5/ADC1535PB0/ADC836PB1/ADC937PB2/BOOT138PE739PE840PE941PE1042PE1143PE1244PE1345PE1446PE1547PB1048PB1149VSS_150VIO_1100VIO_399VSS_398PE197PE096PB995PB894BOOT093PB792PB691PB590PB489PB388PD787PD686PD585PD484PD383PD282PD181PD080PC1279PC1178PC1077PA1576PA14/SWCLK75VDD_274VSS_273NC72PA13/SWDIO71PA12/USB1DP70PA11/USB1DM69PA1068PA967PA866PC965PC864PC763PC662PD1561PD1460PD1359PD1258PD1157PD1056PD955PD854PB1553PB1452PB1351PB12Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100E=14.00mm · Pitch e=0.50mmD=14.00mm-12-10-8-6-4-2024681012121086420-2-4-6-8-10-12mm
3. 3D CAD MODEL
Package Body: 14.00mm × 14.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
2PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
3PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
4PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
5PE6I/OMultiplexed I/O & Peripheral Pin PE6 (General)
6VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
7PC13/TAMPER-RTCI/OMultiplexed I/O & Peripheral Pin PC13/TAMPER-RTC (RTC/CLK)
8PC14/OSC32INI/OMultiplexed I/O & Peripheral Pin PC14/OSC32IN (RTC/CLK)
9PC15/OSC320UTI/OMultiplexed I/O & Peripheral Pin PC15/OSC320UT (RTC/CLK)
10VSS_5GNDGround Reference Pin (VSS_5)
11VDD_5PowerPower Supply Input (VDD_5 — 3.3V / 5.0V Standard Logic)
12OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
13OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
14NRSTISystem Enable & Hardware Reset (NRST)
15PC0/ADC10I/OMultiplexed I/O & Peripheral Pin PC0/ADC10 (ADC)
16PC1/ADC11I/OMultiplexed I/O & Peripheral Pin PC1/ADC11 (ADC)
17PC2/ADC12I/OMultiplexed I/O & Peripheral Pin PC2/ADC12 (ADC)
18PC3/ADC13I/OMultiplexed I/O & Peripheral Pin PC3/ADC13 (ADC)
19VSSAGNDGround Reference Pin (VSSA)
20VREF-AnalogMultiplexed I/O & Peripheral Pin VREF- (General)
21VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
22VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
23PA0/WKUP/ADC0I/OMultiplexed I/O & Peripheral Pin PA0/WKUP/ADC0 (ADC)
24PA1/ADC1I/OMultiplexed I/O & Peripheral Pin PA1/ADC1 (ADC)
25PA2/ADC2I/OMultiplexed I/O & Peripheral Pin PA2/ADC2 (ADC)
26PA3/ADC3I/OMultiplexed I/O & Peripheral Pin PA3/ADC3 (ADC)
27VSS_4GNDGround Reference Pin (VSS_4)
28VDD_4PowerPower Supply Input (VDD_4 — 3.3V / 5.0V Standard Logic)
29PA4/ADC4/DAC0I/OMultiplexed I/O & Peripheral Pin PA4/ADC4/DAC0 (ADC, DAC)
30PA5/ADC5/DAC1I/OMultiplexed I/O & Peripheral Pin PA5/ADC5/DAC1 (ADC, DAC)
31PA6/ADC6I/OMultiplexed I/O & Peripheral Pin PA6/ADC6 (ADC)
32PA7/ADC7I/OMultiplexed I/O & Peripheral Pin PA7/ADC7 (ADC)
33PC4/ADC14I/OMultiplexed I/O & Peripheral Pin PC4/ADC14 (ADC)
34PC5/ADC15I/OMultiplexed I/O & Peripheral Pin PC5/ADC15 (ADC)
35PB0/ADC8I/OMultiplexed I/O & Peripheral Pin PB0/ADC8 (ADC)
36PB1/ADC9I/OMultiplexed I/O & Peripheral Pin PB1/ADC9 (ADC)
37PB2/BOOT1I/OMultiplexed I/O & Peripheral Pin PB2/BOOT1 (General)
38PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
39PE8I/OMultiplexed I/O & Peripheral Pin PE8 (General)
40PE9I/OMultiplexed I/O & Peripheral Pin PE9 (General)
41PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
42PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
43PE12I/OMultiplexed I/O & Peripheral Pin PE12 (General)
44PE13I/OMultiplexed I/O & Peripheral Pin PE13 (General)
45PE14I/OMultiplexed I/O & Peripheral Pin PE14 (General)
46PE15I/OMultiplexed I/O & Peripheral Pin PE15 (General)
47PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
48PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
49VSS_1GNDExposed Thermal & Ground Pad (VSS_1)
50VIO_1I/OMultiplexed I/O & Peripheral Pin VIO_1 (General)
51PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
52PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
53PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
54PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
55PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
56PD9I/OMultiplexed I/O & Peripheral Pin PD9 (General)
57PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
58PD11I/OMultiplexed I/O & Peripheral Pin PD11 (General)
59PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
60PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
61PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
62PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
63PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
64PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
65PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
66PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
67PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
68PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
69PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
70PA11/USB1DMI/OMultiplexed I/O & Peripheral Pin PA11/USB1DM (USB)
71PA12/USB1DPI/OMultiplexed I/O & Peripheral Pin PA12/USB1DP (USB)
72PA13/SWDIOI/OMultiplexed I/O & Peripheral Pin PA13/SWDIO (SWD/JTAG)
73NCI/OMultiplexed I/O & Peripheral Pin NC (General)
74VSS_2GNDGround Reference Pin (VSS_2)
75VDD_2PowerPower Supply Input (VDD_2 — 3.3V / 5.0V Standard Logic)
76PA14/SWCLKI/OMultiplexed I/O & Peripheral Pin PA14/SWCLK (SWD/JTAG)
77PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
78PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
79PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
80PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
81PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
82PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
83PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
84PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
85PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
86PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
87PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
88PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
89PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
90PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
91PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
92PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
93PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
94BOOT0IInput-Only Pin BOOT0 (General)
95PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
96PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
97PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
98PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
99VSS_3GNDGround Reference Pin (VSS_3)
100VIO_3I/OMultiplexed I/O & Peripheral Pin VIO_3 (General)
PIN 1 PE2
I/O
Multiplexed I/O & Peripheral Pin PE2 (General)
Design note: Signal terminal PE2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 4 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32V303VCT6 (WCH · LQFP-100(14x14))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32V303VCT6 (LQFP-100(14x14)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32V303VCT6 (LQFP-100(14x14)) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32V303VCT6 (LQFP-100(14x14)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32V303VCT6 (LQFP-100(14x14)) - 4. Package Dimensions (D×E×A)
LQFP-100(14x14) · 14.00×14.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32V303VCT6 (LQFP-100(14x14)) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32V303VCT6 (LQFP-100(14x14)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (4 figures · Page 1/1)
Showing 1–4 of 4 uncropped original figures for CH32V208 / CH32V305 / CH32V307
P1 · p01_fig01245×133px
CH32V303VCT6 (LQFP-100(14x14)) — Overview
Overview
P40 · p40_fig011708×672px
CH32V303VCT6 (LQFP-100(14x14)) — Table 8-13 Rounding Mode | Rounding code Rounding mode Description | 000 RNE Rounding to the nearest value, even values are preferred | 001 RTZ Rounding to zero | 010 RDN Rounding down (to -∞) | 011 RUP Rounding up (to ∞) | 100 RMM Round to
Table 8-13 Rounding Mode | Rounding code Rounding mode Description | 000 RNE Rounding to the nearest value, even values are preferred | 001 RTZ Rounding to zero | 010 RDN Rounding down (to -∞) | 011 RUP Rounding up (to ∞) | 100 RMM Round to
P42 · p42_fig011708×323px
CH32V303VCT6 (LQFP-100(14x14)) — The cache operation control register is mainly used to clear or invalidate instructions or data in the cache.
The cache operation control register is mainly used to clear or invalidate instructions or data in the cache.
P42 · p42_fig021727×2107px
CH32V303VCT6 (LQFP-100(14x14)) — V1.3 41
V1.3 41

Technical Specifications & Part Details (CH32V303VCT6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:CH32V303VCT6 (LQFP-100(14x14)) is a 100-pin embedded microcontroller unit (mcu) featuring a 14.00 × 14.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated ADC, DAC, RTC/CLK, SWD/JTAG, USB interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
14.00 × 14.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-100(14x14))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
ADC, DAC, RTC/CLK, SWD/JTAG, USB
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2/BOOT1, BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-100(14x14))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
14.00 × 14.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
100P / 100Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-100(14x14)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32V303VCT6 (LQFP-100(14x14))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32V303VCT6 (LQFP-100(14x14))?

Manufactured by WCH, the CH32V303VCT6 is housed in a LQFP-100(14x14) package with 100 pins and a 0.50 mm lead pitch. Key pins include: 1 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), 2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), 3 (PE4: Multiplexed I/O & Peripheral Pin PE4 (General)), 4 (PE5: Multiplexed I/O & Peripheral Pin PE5 (General)), 5 (PE6: Multiplexed I/O & Peripheral Pin PE6 (General)), 6 (VBAT: Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)).

What are the IPC-7351B PCB Footprint dimensions for CH32V303VCT6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32V303VCT6 (LQFP-100(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32V303VCT6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32V303VCT6 (WCH, LQFP-100(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & CH32V208 / CH32V305 / CH32V307 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PE2Digital_IOSignal terminal PE2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
2PE3Digital_IOSignal terminal PE3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
3PE4Digital_IOSignal terminal PE4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
4PE5Digital_IOSignal terminal PE5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
5PE6Digital_IOSignal terminal PE6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
6VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
7PC13/TAMPER-RTCDigital_IOSignal terminal PC13/TAMPER-RTC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13/TAMPER-RTC. Supported peripheral buses: RTC/CLK.
8PC14/OSC32INDigital_IOSignal terminal PC14/OSC32IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14/OSC32IN. Supported peripheral buses: RTC/CLK.
9PC15/OSC320UTDigital_IOSignal terminal PC15/OSC320UT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC15/OSC320UT. Supported peripheral buses: RTC/CLK.
10VSS_5GND0V electrical ground return terminal (VSS_5) for internal core logic, I/O drivers, and analog sub-blocks.
11VDD_5Power_InPrimary positive power supply input (VDD_5) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
12OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
13OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
14NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
15PC0/ADC10AnalogSignal terminal PC0/ADC10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0/ADC10. Supported peripheral buses: ADC.
16PC1/ADC11AnalogSignal terminal PC1/ADC11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1/ADC11. Supported peripheral buses: ADC.
17PC2/ADC12AnalogSignal terminal PC2/ADC12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2/ADC12. Supported peripheral buses: ADC.
18PC3/ADC13AnalogSignal terminal PC3/ADC13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3/ADC13. Supported peripheral buses: ADC.
19VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
20VREF-AnalogSignal terminal VREF- (Analog, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VREF-. Supported peripheral buses: General.
21VREF+AnalogSignal terminal VREF+ (Analog, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
22VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
23PA0/WKUP/ADC0AnalogSignal terminal PA0/WKUP/ADC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0/WKUP/ADC0. Supported peripheral buses: ADC.
24PA1/ADC1AnalogSignal terminal PA1/ADC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1/ADC1. Supported peripheral buses: ADC.
25PA2/ADC2AnalogSignal terminal PA2/ADC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2/ADC2. Supported peripheral buses: ADC.
26PA3/ADC3AnalogSignal terminal PA3/ADC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3/ADC3. Supported peripheral buses: ADC.
27VSS_4GND0V electrical ground return terminal (VSS_4) for internal core logic, I/O drivers, and analog sub-blocks.
28VDD_4Power_InPrimary positive power supply input (VDD_4) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
29PA4/ADC4/DAC0AnalogSignal terminal PA4/ADC4/DAC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4/ADC4/DAC0. Supported peripheral buses: ADC, DAC.
30PA5/ADC5/DAC1AnalogSignal terminal PA5/ADC5/DAC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5/ADC5/DAC1. Supported peripheral buses: ADC, DAC.
31PA6/ADC6AnalogSignal terminal PA6/ADC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6/ADC6. Supported peripheral buses: ADC.
32PA7/ADC7AnalogSignal terminal PA7/ADC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7/ADC7. Supported peripheral buses: ADC.
33PC4/ADC14AnalogSignal terminal PC4/ADC14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4/ADC14. Supported peripheral buses: ADC.
34PC5/ADC15AnalogSignal terminal PC5/ADC15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5/ADC15. Supported peripheral buses: ADC.
35PB0/ADC8AnalogSignal terminal PB0/ADC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0/ADC8. Supported peripheral buses: ADC.
36PB1/ADC9AnalogSignal terminal PB1/ADC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1/ADC9. Supported peripheral buses: ADC.
37PB2/BOOT1Digital_IOSignal terminal PB2/BOOT1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2/BOOT1. Supported peripheral buses: General.
38PE7Digital_IOSignal terminal PE7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General.
39PE8Digital_IOSignal terminal PE8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE8. Supported peripheral buses: General.
40PE9Digital_IOSignal terminal PE9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE9. Supported peripheral buses: General.
41PE10Digital_IOSignal terminal PE10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE10. Supported peripheral buses: General.
42PE11Digital_IOSignal terminal PE11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE11. Supported peripheral buses: General.
43PE12Digital_IOSignal terminal PE12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE12. Supported peripheral buses: General.
44PE13Digital_IOSignal terminal PE13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE13. Supported peripheral buses: General.
45PE14Digital_IOSignal terminal PE14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE14. Supported peripheral buses: General.
46PE15Digital_IOSignal terminal PE15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE15. Supported peripheral buses: General.
47PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
48PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
49VSS_1GNDBottom exposed die attach pad (VSS_1) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
50VIO_1Digital_IOSignal terminal VIO_1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO_1. Supported peripheral buses: General.
51PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
52PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
53PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
54PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
55PD8Digital_IOSignal terminal PD8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD8. Supported peripheral buses: General.
56PD9Digital_IOSignal terminal PD9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD9. Supported peripheral buses: General.
57PD10Digital_IOSignal terminal PD10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD10. Supported peripheral buses: General.
58PD11Digital_IOSignal terminal PD11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD11. Supported peripheral buses: General.
59PD12Digital_IOSignal terminal PD12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD12. Supported peripheral buses: General.
60PD13Digital_IOSignal terminal PD13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD13. Supported peripheral buses: General.
61PD14Digital_IOSignal terminal PD14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD14. Supported peripheral buses: General.
62PD15Digital_IOSignal terminal PD15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD15. Supported peripheral buses: General.
63PC6Digital_IOSignal terminal PC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
64PC7Digital_IOSignal terminal PC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
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