Mechanical Dimensions & Land Pattern (LQFP-100(14x14))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
14.00 × 14.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
100P / 100Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-100(14x14) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH32V317VCT6 (LQFP-100(14x14))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH32V317VCT6 (LQFP-100(14x14))?
Manufactured by WCH, the CH32V317VCT6 is housed in a LQFP-100(14x14) package with 100 pins and a 0.50 mm lead pitch. Key pins include: 1 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), 2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), 3 (PE4: Multiplexed I/O & Peripheral Pin PE4 (General)), 4 (PE5: Multiplexed I/O & Peripheral Pin PE5 (General)), 5 (PE6: Multiplexed I/O & Peripheral Pin PE6 (General)), 6 (VBAT: Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)).
What are the IPC-7351B PCB Footprint dimensions for CH32V317VCT6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32V317VCT6 (LQFP-100(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32V317VCT6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32V317VCT6 (WCH, LQFP-100(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (100 pins) & CH32V208 / CH32V305 / CH32V307 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PE2 | Digital_IO | Signal terminal PE2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General. |
| 2 | PE3 | Digital_IO | Signal terminal PE3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General. |
| 3 | PE4 | Digital_IO | Signal terminal PE4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General. |
| 4 | PE5 | Digital_IO | Signal terminal PE5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General. |
| 5 | PE6 | Digital_IO | Signal terminal PE6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General. |
| 6 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 7 | PC13/TAMPER-RTC | Digital_IO | Signal terminal PC13/TAMPER-RTC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13/TAMPER-RTC. Supported peripheral buses: RTC/CLK. |
| 8 | PC14/OSC32IN | Digital_IO | Signal terminal PC14/OSC32IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14/OSC32IN. Supported peripheral buses: RTC/CLK. |
| 9 | PC15/OSC32OUT | Digital_IO | Signal terminal PC15/OSC32OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC15/OSC32OUT. Supported peripheral buses: RTC/CLK. |
| 10 | VSS_5 | GND | 0V electrical ground return terminal (VSS_5) for internal core logic, I/O drivers, and analog sub-blocks. |
| 11 | VDD_5 | Power_In | Primary positive power supply input (VDD_5) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 12 | OSC_IN | Digital_IO | Signal terminal OSC_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK. |
| 13 | OSC_OUT | Digital_IO | Signal terminal OSC_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK. |
| 14 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| 15 | PC0/ADC10 | Analog | Signal terminal PC0/ADC10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0/ADC10. Supported peripheral buses: ADC. |
| 16 | PC1/ADC11 | Analog | Signal terminal PC1/ADC11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1/ADC11. Supported peripheral buses: ADC. |
| 17 | PC2/ADC12 | Analog | Signal terminal PC2/ADC12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2/ADC12. Supported peripheral buses: ADC. |
| 18 | PC3/ADC13 | Analog | Signal terminal PC3/ADC13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3/ADC13. Supported peripheral buses: ADC. |
| 19 | VSSA | GND | 0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks. |
| 20 | VREF- | Analog | Signal terminal VREF- (Analog, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VREF-. Supported peripheral buses: General. |
| 21 | VREF+ | Analog | Signal terminal VREF+ (Analog, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General. |
| 22 | VDDA | Power_In | Primary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 23 | PA0/WKUP/ADC0 | Analog | Signal terminal PA0/WKUP/ADC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0/WKUP/ADC0. Supported peripheral buses: ADC. |
| 24 | PA1/ADC1 | Analog | Signal terminal PA1/ADC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1/ADC1. Supported peripheral buses: ADC. |
| 25 | PA2/ADC2 | Analog | Signal terminal PA2/ADC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2/ADC2. Supported peripheral buses: ADC. |
| 26 | PA3/ADC3 | Analog | Signal terminal PA3/ADC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3/ADC3. Supported peripheral buses: ADC. |
| 27 | VSS_4 | GND | 0V electrical ground return terminal (VSS_4) for internal core logic, I/O drivers, and analog sub-blocks. |
| 28 | VIO_4 | Digital_IO | Signal terminal VIO_4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO_4. Supported peripheral buses: General. |
| 29 | PA4/ADC4/DAC0 | Analog | Signal terminal PA4/ADC4/DAC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4/ADC4/DAC0. Supported peripheral buses: ADC, DAC. |
| 30 | PA5/ADC5/DAC1 | Analog | Signal terminal PA5/ADC5/DAC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5/ADC5/DAC1. Supported peripheral buses: ADC, DAC. |
| 31 | PA6/ADC6 | Analog | Signal terminal PA6/ADC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6/ADC6. Supported peripheral buses: ADC. |
| 32 | PA7/ADC7 | Analog | Signal terminal PA7/ADC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7/ADC7. Supported peripheral buses: ADC. |
| 33 | PC4/ADC14 | Analog | Signal terminal PC4/ADC14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4/ADC14. Supported peripheral buses: ADC. |
| 34 | PC5/ADC15 | Analog | Signal terminal PC5/ADC15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5/ADC15. Supported peripheral buses: ADC. |
| 35 | PB0/ADC8 | Analog | Signal terminal PB0/ADC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0/ADC8. Supported peripheral buses: ADC. |
| 36 | PB1/ADC9 | Analog | Signal terminal PB1/ADC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1/ADC9. Supported peripheral buses: ADC. |
| 37 | PB2/BOOT1 | Digital_IO | Signal terminal PB2/BOOT1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2/BOOT1. Supported peripheral buses: General. |
| 38 | LED0 | Digital_IO | Signal terminal LED0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED0. Supported peripheral buses: General. |
| 39 | LED1 | Digital_IO | Signal terminal LED1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED1. Supported peripheral buses: General. |
| 40 | VDDK | Power_In | Primary positive power supply input (VDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 41 | VSS_6 | GND | 0V electrical ground return terminal (VSS_6) for internal core logic, I/O drivers, and analog sub-blocks. |
| 42 | MDITP | Digital_IO | Signal terminal MDITP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITP. Supported peripheral buses: General. |
| 43 | MDITN | Digital_IO | Signal terminal MDITN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITN. Supported peripheral buses: General. |
| 44 | MDIRP | Digital_IO | Signal terminal MDIRP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRP. Supported peripheral buses: General. |
| 45 | MDIRN | Digital_IO | Signal terminal MDIRN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRN. Supported peripheral buses: General. |
| 46 | VDD_ETH | Power_In | Primary positive power supply input (VDD_ETH) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 47 | VSS_1 | GND | 0V electrical ground return terminal (VSS_1) for internal core logic, I/O drivers, and analog sub-blocks. |
| 48 | VIO_1 | Digital_IO | Signal terminal VIO_1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO_1. Supported peripheral buses: General. |
| 49 | PB10 | Digital_IO | Signal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General. |
| 50 | PB11 | Digital_IO | Signal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General. |
| 51 | VDD_1 | Power_In | Primary positive power supply input (VDD_1) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 52 | PB12 | Digital_IO | Signal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General. |
| 53 | PB13 | Digital_IO | Signal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General. |
| 54 | PB14 | Digital_IO | Signal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General. |
| 55 | PB15 | Digital_IO | Signal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General. |
| 56 | PD9 | Digital_IO | Signal terminal PD9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD9. Supported peripheral buses: General. |
| 57 | PD10 | Digital_IO | Signal terminal PD10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD10. Supported peripheral buses: General. |
| 58 | PD11 | Digital_IO | Signal terminal PD11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD11. Supported peripheral buses: General. |
| 59 | PD12 | Digital_IO | Signal terminal PD12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD12. Supported peripheral buses: General. |
| 60 | PD13 | Digital_IO | Signal terminal PD13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD13. Supported peripheral buses: General. |
| 61 | PD14 | Digital_IO | Signal terminal PD14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD14. Supported peripheral buses: General. |
| 62 | PD15 | Digital_IO | Signal terminal PD15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD15. Supported peripheral buses: General. |
| 63 | PC6/RXP | Digital_IO | Signal terminal PC6/RXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC6/RXP. Supported peripheral buses: General. |
| 64 | PC7/RXN | Digital_IO | Signal terminal PC7/RXN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC7/RXN. Supported peripheral buses: General. |