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DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) — Symbol, Footprint IPC-7351B & 3D STEP Model

DSPIC30F2010-30I/MM

MICROCHIPID: C510869QFN-28-EP(6x6) · 29 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · DSPIC30F2010-30I/MM (QFN-28-EP(6x6))1AN2/SS1#/CN42AN3/INDX/CN53AN4/QEA/IC7/4AN5/QEB/IC8/5VSS6OSC1/CLKI7OSC2/CLKO/RC8IO09IO410VDD11EMUD2/OC2/IC12EMUC2/OC1/IC13IO1514IO1615IO1729EP28IO3327IO4726MCLR#25AVDD24AVSS23PWM1L/RE022PWM1H/RE121PWM2L/RE220PWM2H/RE319PWM3L/RE418PWM3H/RE517VDD16VSSGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.825.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829E=6.00mm · Pitch e=0.65mmD=6.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 6.00mm × 6.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1AN2/SS1#/CN4/RB2I/OMultiplexed I/O & Peripheral Pin AN2/SS1#/CN4/RB2 (General)
2AN3/INDX/CN5/RB3I/OMultiplexed I/O & Peripheral Pin AN3/INDX/CN5/RB3 (General)
3AN4/QEA/IC7/CN6/RB4I/OMultiplexed I/O & Peripheral Pin AN4/QEA/IC7/CN6/RB4 (General)
4AN5/QEB/IC8/CN7/RB5I/OMultiplexed I/O & Peripheral Pin AN5/QEB/IC8/CN7/RB5 (General)
5VSSGNDGround Reference Pin (VSS)
6OSC1/CLKII/OMultiplexed I/O & Peripheral Pin OSC1/CLKI (RTC/CLK)
7OSC2/CLKO/RC15I/OMultiplexed I/O & Peripheral Pin OSC2/CLKO/RC15 (RTC/CLK)
8IO0I/OGPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9IO4I/OGPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10VDDPowerPower Supply Input (VDD — 2.5V to 5.5V)
11EMUD2/OC2/IC2/INT2/RD1I/OMultiplexed I/O & Peripheral Pin EMUD2/OC2/IC2/INT2/RD1 (General)
12EMUC2/OC1/IC1/INT1/RD0I/OMultiplexed I/O & Peripheral Pin EMUC2/OC1/IC1/INT1/RD0 (General)
13IO15I/OGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14IO16I/OGPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15IO17I/OGPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6
16VSSGNDGround Reference Pin (VSS)
17VDDPowerPower Supply Input (VDD — 2.5V to 5.5V)
18PWM3H/RE5I/OMultiplexed I/O & Peripheral Pin PWM3H/RE5 (PWM)
19PWM3L/RE4I/OMultiplexed I/O & Peripheral Pin PWM3L/RE4 (PWM)
20PWM2H/RE3I/OMultiplexed I/O & Peripheral Pin PWM2H/RE3 (PWM)
21PWM2L/RE2I/OMultiplexed I/O & Peripheral Pin PWM2L/RE2 (PWM)
22PWM1H/RE1I/OMultiplexed I/O & Peripheral Pin PWM1H/RE1 (PWM)
23PWM1L/RE0I/OMultiplexed I/O & Peripheral Pin PWM1L/RE0 (PWM)
24AVSSGNDGround Reference Pin (AVSS)
25AVDDPowerPower Supply Input (AVDD — 2.5V to 5.5V)
26MCLR#I/OMultiplexed I/O & Peripheral Pin MCLR# (General)
27IO47I/OGPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF
28IO33I/OGPIO33 / FSPIHD / SUBSPIHD / SPIIO4
29EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 AN2/SS1#/CN4/RB2
I/O
Multiplexed I/O & Peripheral Pin AN2/SS1#/CN4/RB2 (General)
Design note: Signal terminal AN2/SS1#/CN4/RB2 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: AN2/SS1#/CN4/RB2. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: DSPIC30F2010-30I/MM (MICROCHIP · QFN-28-EP(6x6))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) - 4. Package Dimensions (D×E×A)
QFN-28-EP(6x6) · 6.00×6.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)
Showing 1–12 of 15 uncropped original figures for DSPIC30F2010
P1 · p01_fig01752×399px
DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) — dsPIC30F2010
dsPIC30F2010
P1 · p01_fig01P1
DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P2 · p02_fig011777×1639px
DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) — DS70118J-page 2 © 2011 Microchip Technology Inc. | Trademarks | FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Inc
DS70118J-page 2 © 2011 Microchip Technology Inc. | Trademarks | FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Inc
P2 · p02_fig02785×283px
DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) — ISBN: 978-1-60932-889-4
ISBN: 978-1-60932-889-4
P43 · p43_fig011778×917px
DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) — The TBLRDL and the TBLWTL instructions are used to read or write to bits<15:0> of program memory. TBLRDL and TBLWTL can access program memory in Word or Byte mode.
The TBLRDL and the TBLWTL instructions are used to read or write to bits<15:0> of program memory. TBLRDL and TBLWTL can access program memory in Word or Byte mode.
P43 · p43_fig021246×917px
DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) — FIGURE 6-1: ADDRESSING FOR TABLE AND NVM REGISTERS
FIGURE 6-1: ADDRESSING FOR TABLE AND NVM REGISTERS
P95 · p95_fig011174×666px
DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) — FIGURE 16-1: PROGRAMMER’S MODEL
FIGURE 16-1: PROGRAMMER’S MODEL
P95 · p95_fig01P95
DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) — Datasheet Page 95 (p95_fig01)
Datasheet Page 95 (p95_fig01)
P114 · p114_fig01867×790px
DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) — FIGURE 18-2: ADC VOLTAGE REFERENCE SCHEMATIC
FIGURE 18-2: ADC VOLTAGE REFERENCE SCHEMATIC
P114 · p114_fig01P114
DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) — Datasheet Page 114 (p114_fig01)
Datasheet Page 114 (p114_fig01)
P115 · p115_fig011780×2327px
DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) — dsPIC30F2010 | TABLE 18-1: 10-BIT A/D CONVERSION RATE PARAMETERS | dsPIC30F 10-bit A/D Converter Conversion Rates | A/D Speed TAD Minimum | Sampling | Time Min RS Max VDD Temperature A/D Channels Configuration | Up to 1 Msps(1) 83.33 ns 12
dsPIC30F2010 | TABLE 18-1: 10-BIT A/D CONVERSION RATE PARAMETERS | dsPIC30F 10-bit A/D Converter Conversion Rates | A/D Speed TAD Minimum | Sampling | Time Min RS Max VDD Temperature A/D Channels Configuration | Up to 1 Msps(1) 83.33 ns 12
P185 · p185_fig021361×615px
DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) — © 2011 Microchip Technology Inc. DS70118J-page 185
© 2011 Microchip Technology Inc. DS70118J-page 185
Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (DSPIC30F2010-30I/MM)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) is a 28-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 2.5V to 5.5V supply operation across -40°C to 85°C with integrated UART, SPI, ADC, PWM, I2C, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
2.5V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
40 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 6.00 × 1.00 mm (A1=0.03 mm)
Package family: QFN (QFN-28-EP(6x6))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, ADC, PWM, I2C, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteEPAD 4.70×4.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-28-EP(6x6))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.65mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-28-EP(6x6)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — DSPIC30F2010-30I/MM (QFN-28-EP(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of DSPIC30F2010-30I/MM (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the DSPIC30F2010-30I/MM is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.5V to 5.5V. Key pins include: 1 (AN2/SS1#/CN4/RB2: Multiplexed I/O & Peripheral Pin AN2/SS1#/CN4/RB2 (General)), 2 (AN3/INDX/CN5/RB3: Multiplexed I/O & Peripheral Pin AN3/INDX/CN5/RB3 (General)), 3 (AN4/QEA/IC7/CN6/RB4: Multiplexed I/O & Peripheral Pin AN4/QEA/IC7/CN6/RB4 (General)), 4 (AN5/QEB/IC8/CN7/RB5: Multiplexed I/O & Peripheral Pin AN5/QEB/IC8/CN7/RB5 (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (OSC1/CLKI: Multiplexed I/O & Peripheral Pin OSC1/CLKI (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for DSPIC30F2010-30I/MM?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), DSPIC30F2010-30I/MM (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for DSPIC30F2010-30I/MM?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for DSPIC30F2010-30I/MM (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & DSPIC30F2010 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1AN2/SS1#/CN4/RB2Digital_IOSignal terminal AN2/SS1#/CN4/RB2 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: AN2/SS1#/CN4/RB2. Supported peripheral buses: General.
2AN3/INDX/CN5/RB3Digital_IOSignal terminal AN3/INDX/CN5/RB3 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: AN3/INDX/CN5/RB3. Supported peripheral buses: General.
3AN4/QEA/IC7/CN6/RB4Digital_IOSignal terminal AN4/QEA/IC7/CN6/RB4 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: AN4/QEA/IC7/CN6/RB4. Supported peripheral buses: General.
4AN5/QEB/IC8/CN7/RB5Digital_IOSignal terminal AN5/QEB/IC8/CN7/RB5 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: AN5/QEB/IC8/CN7/RB5. Supported peripheral buses: General.
5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
6OSC1/CLKIDigital_IOSignal terminal OSC1/CLKI (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: OSC1/CLKI. Supported peripheral buses: RTC/CLK.
7OSC2/CLKO/RC15Digital_IOSignal terminal OSC2/CLKO/RC15 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: OSC2/CLKO/RC15. Supported peripheral buses: RTC/CLK.
8IO0Digital_IOGPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9IO4Digital_IOGPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10VDDPower_InPrimary positive power supply input (VDD) operating in the 2.5V to 5.5V domain (Max rating: 5.5V).
11EMUD2/OC2/IC2/INT2/RD1Digital_IOSignal terminal EMUD2/OC2/IC2/INT2/RD1 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: EMUD2/OC2/IC2/INT2/RD1. Supported peripheral buses: General.
12EMUC2/OC1/IC1/INT1/RD0Digital_IOSignal terminal EMUC2/OC1/IC1/INT1/RD0 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: EMUC2/OC1/IC1/INT1/RD0. Supported peripheral buses: General.
13IO15Digital_IOGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14IO16Digital_IOGPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15IO17Digital_IOGPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6
16VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
17VDDPower_InPrimary positive power supply input (VDD) operating in the 2.5V to 5.5V domain (Max rating: 5.5V).
18PWM3H/RE5Digital_IOSignal terminal PWM3H/RE5 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: PWM3H/RE5. Supported peripheral buses: PWM.
19PWM3L/RE4Digital_IOSignal terminal PWM3L/RE4 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: PWM3L/RE4. Supported peripheral buses: PWM.
20PWM2H/RE3Digital_IOSignal terminal PWM2H/RE3 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: PWM2H/RE3. Supported peripheral buses: PWM.
21PWM2L/RE2Digital_IOSignal terminal PWM2L/RE2 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: PWM2L/RE2. Supported peripheral buses: PWM.
22PWM1H/RE1Digital_IOSignal terminal PWM1H/RE1 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: PWM1H/RE1. Supported peripheral buses: PWM.
23PWM1L/RE0Digital_IOSignal terminal PWM1L/RE0 (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: PWM1L/RE0. Supported peripheral buses: PWM.
24AVSSGND0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
25AVDDPower_InPrimary positive power supply input (AVDD) operating in the 2.5V to 5.5V domain (Max rating: 5.5V).
26MCLR#Digital_IOSignal terminal MCLR# (I/O, 2.5V to 5.5V domain). Multiplexed alternate functions: MCLR#. Supported peripheral buses: General.
27IO47Digital_IOGPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF
28IO33Digital_IOGPIO33 / FSPIHD / SUBSPIHD / SPIIO4
29EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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