ATTINY24-20MU (QFN-20-EP(4x4)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of ATTINY24-20MU (QFN-20-EP(4x4))?

Manufactured by MICROCHIP, the ATTINY24-20MU is housed in a QFN-20-EP(4x4) package with 21 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.8V to 5.5V. Key pins include: 1 (1: Multiplexed I/O & Peripheral Pin 1 (I2C)), 2 ((ADC3/T0/PCINT3)PA3: Multiplexed I/O & Peripheral Pin (ADC3/T0/PCINT3)PA3 (ADC)), 3 ((ADC2/AIN1/PCINT2)PA2: Multiplexed I/O & Peripheral Pin (ADC2/AIN1/PCINT2)PA2 (ADC)), 4 ((ADC1/AIN0/PCINT1)PA1: Multiplexed I/O & Peripheral Pin (ADC1/AIN0/PCINT1)PA1 (ADC)), 5 ((ADC0/AREF/PCINT0)PA0: Multiplexed I/O & Peripheral Pin (ADC0/AREF/PCINT0)PA0 (ADC)), 6 (DNC: Multiplexed I/O & Peripheral Pin DNC (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for ATTINY24-20MU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATTINY24-20MU (QFN-20-EP(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 2.50 × 2.50 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATTINY24-20MU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATTINY24-20MU (MICROCHIP, QFN-20-EP(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 4.00mm × 4.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (21/21)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	1	I/O	Multiplexed I/O & Peripheral Pin 1 (I2C)
2	(ADC3/T0/PCINT3)PA3	I/O	Multiplexed I/O & Peripheral Pin (ADC3/T0/PCINT3)PA3 (ADC)
3	(ADC2/AIN1/PCINT2)PA2	I/O	Multiplexed I/O & Peripheral Pin (ADC2/AIN1/PCINT2)PA2 (ADC)
4	(ADC1/AIN0/PCINT1)PA1	I/O	Multiplexed I/O & Peripheral Pin (ADC1/AIN0/PCINT1)PA1 (ADC)
5	(ADC0/AREF/PCINT0)PA0	I/O	Multiplexed I/O & Peripheral Pin (ADC0/AREF/PCINT0)PA0 (ADC)
6	DNC	I/O	Multiplexed I/O & Peripheral Pin DNC (General)
7	DNC	I/O	Multiplexed I/O & Peripheral Pin DNC (General)
8	GND	GND	Ground Reference Pin (GND)
9	VCC	Power	Power Supply Input (VCC — 1.8V to 5.5V)
10	DNC	I/O	Multiplexed I/O & Peripheral Pin DNC (General)
11	PB0(PCINT8/XTAL1/CLKI)	I/O	Multiplexed I/O & Peripheral Pin PB0(PCINT8/XTAL1/CLKI) (RTC/CLK)
12	PB1(PCINT9/XTAL2)	I/O	Multiplexed I/O & Peripheral Pin PB1(PCINT9/XTAL2) (RTC/CLK)
13	PB3(PCINT11/#RESET/dW)	I	System Enable & Hardware Reset (PB3(PCINT11/#RESET/dW))
14	IO16	I/O	GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15	IO17	I/O	GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6
16	IO18	I/O	GPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3
17	DNC	I/O	Multiplexed I/O & Peripheral Pin DNC (General)
18	DNC	I/O	Multiplexed I/O & Peripheral Pin DNC (General)
19	DNC	I/O	Multiplexed I/O & Peripheral Pin DNC (General)
20	IO9	I/O	GPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD
21	EP	GND	Exposed Thermal & Ground Pad (EP)

PIN 1 1

I/O

Multiplexed I/O & Peripheral Pin 1 (I2C)

Design note: Two-wire mode Uses SDA and SCL pins . . Same operation as in two-wire mode above except that the SCL line is also , heldlowwhenacounteroverflowoccurs anduntiltheCounterOverflowFlag , (USIOIF)iscleared .

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

ATTINY24-20MU (QFN-20-EP(4x4)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

ATTINY24-20MU (QFN-20-EP(4x4)) - 2. Standard Pinout (Top View)

True package pinout (21 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

ATTINY24-20MU (QFN-20-EP(4x4)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

ATTINY24-20MU (QFN-20-EP(4x4)) - 4. Package Dimensions (D×E×A)

QFN-20-EP(4x4) · 4.00×4.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

ATTINY24-20MU (QFN-20-EP(4x4)) - 5. Recommended Land Pattern

IPC-7351B Footprint (21 Pads)Expand ›

6. Application SchematicSCHEMATIC

ATTINY24-20MU (QFN-20-EP(4x4)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)

Showing 1–10 of 10 uncropped original figures for ATTINY24

P1 · p01_fig01652×376px

8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash

P2 · p02_fig011870×1418px

Figure 1-1. Pinout ATtiny24/44/84

P56 · p56_fig011500×861px

Figure 10-3. Synchronization when Reading an Externally Applied Pin value

P56 · p56_fig01P56

Datasheet Page 56 (p56_fig01)

P87 · p87_fig012050×1395px

Figure 12-1. 16-bit Timer/Counter Block Diagram

P175 · p175_fig011429×613px

Figure 20-1. Maximum Frequency vs. VCC (ATtiny24V/44V/84V)

P220 · p220_fig012124×2562px

ATTINY24-20MU (QFN-20-EP(4x4)) — 220 | 8006K-AVR-10/10 ATtiny24/44/84 | 25. Packaging Information | 25.1 20M1 | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, A 20M1 | 10/27/04 | 2.6 mm Exposed

P220 · p220_fig01P220

Datasheet Page 220 (p220_fig01)

P221 · p221_fig01All Packages in PDF

ATTINY24-20MU (QFN-20-EP(4x4)) — 221 | 8006K-AVR-10/10 | ATtiny24/44/84 | 25.2 14P3 | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 14P3, 14-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) A 14P3 | 11/02/05 | PIN | 1 | E1 | A1 | B | E

221 | 8006K-AVR-10/10 | ATtiny24/44/84 | 25.2 14P3 | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 14P3, 14-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) A 14P3 | 11/02/05 | PIN | 1 | E1 | A1 | B | E

P222 · p222_fig01All Packages in PDF

ATTINY24-20MU (QFN-20-EP(4x4)) — 222 | 8006K-AVR-10/10 ATtiny24/44/84 | 25.3 14S1 | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 14S1, 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) | 2/5/02 | 14S1 A | A1 | E | L | Side

222 | 8006K-AVR-10/10 ATtiny24/44/84 | 25.3 14S1 | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 14S1, 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) | 2/5/02 | 14S1 A | A1 | E | L | Side

Technical Specifications & Part Details (ATTINY24-20MU)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:ATTINY24-20MU (QFN-20-EP(4x4)) is a 20-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.80 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V to 5.5V supply operation across -40°C to +85°C with integrated SPI, I2C, ADC, PWM, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V to 5.5V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to +85°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

4 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

4.00 × 4.00 × 0.80 mm (A1=0.03 mm)

Package family: QFN (QFN-20-EP(4x4))

Pin Count & Lead PitchN / e

20 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

SPI, I2C, ADC, PWM, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol21 auto-grouped pins

IPC-7351B Land Pattern21 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteEPAD 2.50×2.50mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

IPC-7351B

Family Variants & Same Datasheet Chips — ATTINY24 (2)

Select package variant or sibling MPN sharing this datasheet

SOIC-14 · 14P

ATTINY24-20SSU

MICROCHIP·SOIC-14

IPC-7351B

14P8.7×3.9×1.75mmP=1.27mm

ATTINY24 (SOIC-14)

QFN-20-EP(4x4) · 21P

ATTINY24-20MU

MICROCHIP·QFN-20-EP(4x4)

IPC-7351B

21P4.0×4.0×0.80mmP=0.5mm

ATTINY24 (QFN-20-EP(4x4))

Mechanical Dimensions & Land Pattern (QFN-20-EP(4x4))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

4.00 × 4.00 mm

Height (A) & Pitch (e)IPC-7351B

A=0.80mm · e=0.50mm

Pad Size (W × L)Level B

0.28 × 0.80 mm

Pins / Total PadsTopology

21P / 21Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit QFN-20-EP(4x4)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ATTINY24-20MU (QFN-20-EP(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ATTINY24-20MU (QFN-20-EP(4x4))?

Manufactured by MICROCHIP, the ATTINY24-20MU is housed in a QFN-20-EP(4x4) package with 21 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.8V to 5.5V. Key pins include: 1 (1: Multiplexed I/O & Peripheral Pin 1 (I2C)), 2 ((ADC3/T0/PCINT3)PA3: Multiplexed I/O & Peripheral Pin (ADC3/T0/PCINT3)PA3 (ADC)), 3 ((ADC2/AIN1/PCINT2)PA2: Multiplexed I/O & Peripheral Pin (ADC2/AIN1/PCINT2)PA2 (ADC)), 4 ((ADC1/AIN0/PCINT1)PA1: Multiplexed I/O & Peripheral Pin (ADC1/AIN0/PCINT1)PA1 (ADC)), 5 ((ADC0/AREF/PCINT0)PA0: Multiplexed I/O & Peripheral Pin (ADC0/AREF/PCINT0)PA0 (ADC)), 6 (DNC: Multiplexed I/O & Peripheral Pin DNC (General)).

What are the IPC-7351B PCB Footprint dimensions for ATTINY24-20MU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATTINY24-20MU (QFN-20-EP(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 2.50 × 2.50 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATTINY24-20MU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATTINY24-20MU (MICROCHIP, QFN-20-EP(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (21 pins) & ATTINY24 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	1	Digital_IO	Signal terminal 1 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: 1. Supported peripheral buses: I2C.
2	(ADC3/T0/PCINT3)PA3	Analog	Signal terminal (ADC3/T0/PCINT3)PA3 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: (ADC3/T0/PCINT3)PA3. Supported peripheral buses: ADC.
3	(ADC2/AIN1/PCINT2)PA2	Analog	Signal terminal (ADC2/AIN1/PCINT2)PA2 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: (ADC2/AIN1/PCINT2)PA2. Supported peripheral buses: ADC.
4	(ADC1/AIN0/PCINT1)PA1	Analog	Signal terminal (ADC1/AIN0/PCINT1)PA1 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: (ADC1/AIN0/PCINT1)PA1. Supported peripheral buses: ADC.
5	(ADC0/AREF/PCINT0)PA0	Analog	Signal terminal (ADC0/AREF/PCINT0)PA0 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: (ADC0/AREF/PCINT0)PA0. Supported peripheral buses: ADC.
6	DNC	NC	Signal terminal DNC (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: DNC. Supported peripheral buses: General.
7	DNC	NC	Signal terminal DNC (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: DNC. Supported peripheral buses: General.
8	GND	GND	0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
9	VCC	Power_In	Primary positive power supply input (VCC) operating in the 1.8V to 5.5V domain (Max rating: 5.5V).
10	DNC	NC	Signal terminal DNC (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: DNC. Supported peripheral buses: General.
11	PB0(PCINT8/XTAL1/CLKI)	Digital_IO	Signal terminal PB0(PCINT8/XTAL1/CLKI) (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: PB0(PCINT8/XTAL1/CLKI). Supported peripheral buses: RTC/CLK.
12	PB1(PCINT9/XTAL2)	Digital_IO	Signal terminal PB1(PCINT9/XTAL2) (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: PB1(PCINT9/XTAL2). Supported peripheral buses: RTC/CLK.
13	PB3(PCINT11/#RESET/dW)	Digital_IO	Active-low hardware reset terminal (PB3(PCINT11/#RESET/dW)): pulling this pin Low resets the processor core and peripherals.
14	IO16	Digital_IO	GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15	IO17	Digital_IO	GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6
16	IO18	Digital_IO	GPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3
17	DNC	NC	Signal terminal DNC (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: DNC. Supported peripheral buses: General.
18	DNC	NC	Signal terminal DNC (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: DNC. Supported peripheral buses: General.
19	DNC	NC	Signal terminal DNC (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: DNC. Supported peripheral buses: General.
20	IO9	Digital_IO	GPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD
21	EP	GND	Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.

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