VFQFPN-68(8x8) · 69P
Synchronized Pinout (Symbol / 2D / 3D) (100/100)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | PE2 | I/O | Multiplexed I/O & Peripheral Pin PE2 (UART, SPI) |
| 2 | PE4 | I/O | Multiplexed I/O & Peripheral Pin PE4 (SPI) |
| 3 | PE5 | I/O | Multiplexed I/O & Peripheral Pin PE5 (SPI) |
| 4 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 5 | VBAT | Power | Power Supply Input (VBAT — 3.3V VDD (Max 4.0V)) |
| 6 | PC13 | I/O | Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK) |
| 7 | PC14 - OSC32_IN | I/O | Multiplexed I/O & Peripheral Pin PC14 - OSC32_IN (RTC/CLK) |
| 8 | VSS | GND | Ground Reference Pin (VSS) |
| 9 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 10 | VLXSMPS | I/O | Multiplexed I/O & Peripheral Pin VLXSMPS (General) |
| 11 | VDDSMPS | Power | Power Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V)) |
| 12 | VFBSMPS | I/O | Multiplexed I/O & Peripheral Pin VFBSMPS (General) |
| 13 | PH0 - OSC_IN | I/O | Multiplexed I/O & Peripheral Pin PH0 - OSC_IN (RTC/CLK) |
| 14 | PH1 - OSC_OUT | I/O | Multiplexed I/O & Peripheral Pin PH1 - OSC_OUT (RTC/CLK) |
| 15 | NRST | I | System Enable & Hardware Reset (NRST) |
| 16 | PC0 | I/O | Multiplexed I/O & Peripheral Pin PC0 (ADC) |
| 17 | PC1 | I/O | Multiplexed I/O & Peripheral Pin PC1 (SPI, I2C, ADC, RTC/CLK) |
| 18 | PC2_C | I/O | Multiplexed I/O & Peripheral Pin PC2_C (ADC) |
| 19 | PC3_C | I/O | Multiplexed I/O & Peripheral Pin PC3_C (ADC) |
| 20 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 21 | VSS | GND | Ground Reference Pin (VSS) |
| 22 | VSSA | GND | Ground Reference Pin (VSSA) |
| 23 | VREF+ | Analog | Multiplexed I/O & Peripheral Pin VREF+ (General) |
| 24 | VDDA | Power | Power Supply Input (VDDA — 3.3V VDD (Max 4.0V)) |
| 25 | PA0 | I/O | Multiplexed I/O & Peripheral Pin PA0 (UART, SPI, ADC, PWM) |
| 26 | PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM) |
| 27 | PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 (UART, SPI, ADC, PWM) |
| 28 | PA3 | I/O | Multiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM) |
| 29 | VSS | GND | Ground Reference Pin (VSS) |
| 30 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 31 | PA4 | I/O | Multiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC) |
| 32 | PA5 | I/O | Multiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM) |
| 33 | PA6 | I/O | Multiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM) |
| 34 | PA7 | I/O | Multiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM) |
| 35 | PC4 | I/O | Multiplexed I/O & Peripheral Pin PC4 (UART, ADC) |
| 36 | PC5 | I/O | Multiplexed I/O & Peripheral Pin PC5 (UART, ADC) |
| 37 | PB0 | I/O | Multiplexed I/O & Peripheral Pin PB0 (UART, ADC, PWM) |
| 38 | PB1 | I/O | Multiplexed I/O & Peripheral Pin PB1 (ADC, PWM) |
| 39 | PB2 | I/O | Multiplexed I/O & Peripheral Pin PB2 (SPI, I2C, RTC/CLK) |
| 40 | PE7 | I/O | Multiplexed I/O & Peripheral Pin PE7 (UART) |
| 41 | PE8 | I/O | Multiplexed I/O & Peripheral Pin PE8 (UART, PWM) |
| 42 | PB10 | I/O | Multiplexed I/O & Peripheral Pin PB10 (UART, SPI, I2C, PWM) |
| 43 | PB11 | I/O | Multiplexed I/O & Peripheral Pin PB11 (UART, I2C, PWM) |
| 44 | VCAP | I/O | Multiplexed I/O & Peripheral Pin VCAP (General) |
| 45 | VSS | GND | Ground Reference Pin (VSS) |
| 46 | VDDLDO | Power | Power Supply Input (VDDLDO — 3.3V VDD (Max 4.0V)) |
| 47 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 48 | PB12 | I/O | Multiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C) |
| 49 | PB13 | I/O | Multiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM) |
| 50 | PB14 | I/O | Multiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM) |
| 51 | PB15 | I/O | Multiplexed I/O & Peripheral Pin PB15 (UART, SPI, PWM, RTC/CLK) |
| 52 | PD8 | I/O | Multiplexed I/O & Peripheral Pin PD8 (UART) |
| 53 | PD9 | I/O | Multiplexed I/O & Peripheral Pin PD9 (UART) |
| 54 | PD10 | I/O | Multiplexed I/O & Peripheral Pin PD10 (UART) |
| 55 | PD11 | I/O | Multiplexed I/O & Peripheral Pin PD11 (UART, SPI, I2C) |
| 56 | PD12 | I/O | Multiplexed I/O & Peripheral Pin PD12 (UART, I2C, PWM) |
| 57 | PD13 | I/O | Multiplexed I/O & Peripheral Pin PD13 (UART, SPI, I2C, PWM) |
| 58 | VSS | GND | Ground Reference Pin (VSS) |
| 59 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 60 | PD14 | I/O | Multiplexed I/O & Peripheral Pin PD14 (UART, PWM) |
| 61 | PD15 | I/O | Multiplexed I/O & Peripheral Pin PD15 (UART, PWM) |
| 62 | PC6 | I/O | Multiplexed I/O & Peripheral Pin PC6 (General) |
| 63 | PC7 | I/O | Multiplexed I/O & Peripheral Pin PC7 (General) |
| 64 | PC8 | I/O | Multiplexed I/O & Peripheral Pin PC8 (General) |
| 65 | PC9 | I/O | Multiplexed I/O & Peripheral Pin PC9 (General) |
| 66 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (General) |
| 67 | PA9 | I/O | Multiplexed I/O & Peripheral Pin PA9 (General) |
| 68 | PA10 | I/O | Multiplexed I/O & Peripheral Pin PA10 (General) |
| 69 | PA11 | I/O | Multiplexed I/O & Peripheral Pin PA11 (General) |
| 70 | PA12 | I/O | Multiplexed I/O & Peripheral Pin PA12 (General) |
| 71 | PA13 | I/O | Multiplexed I/O & Peripheral Pin PA13 (General) |
| 72 | VCAP | I/O | Multiplexed I/O & Peripheral Pin VCAP (General) |
| 73 | VSS | GND | Ground Reference Pin (VSS) |
| 74 | VDDLDO | Power | Power Supply Input (VDDLDO — 3.3V VDD (Max 4.0V)) |
| 75 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 76 | VDD33USB | Power | Power Supply Input (VDD33USB — 3.3V VDD (Max 4.0V)) |
| 77 | PA14 | I/O | Multiplexed I/O & Peripheral Pin PA14 (General) |
| 78 | PA15 | I/O | Multiplexed I/O & Peripheral Pin PA15 (General) |
| 79 | PC10 | I/O | Multiplexed I/O & Peripheral Pin PC10 (General) |
| 80 | PC11 | I/O | Multiplexed I/O & Peripheral Pin PC11 (General) |
| 81 | PC12 | I/O | Multiplexed I/O & Peripheral Pin PC12 (General) |
| 82 | PD0 | I/O | Multiplexed I/O & Peripheral Pin PD0 (General) |
| 83 | PD1 | I/O | Multiplexed I/O & Peripheral Pin PD1 (General) |
| 84 | PD2 | I/O | Multiplexed I/O & Peripheral Pin PD2 (General) |
| 85 | PD3 | I/O | Multiplexed I/O & Peripheral Pin PD3 (General) |
| 86 | PD4 | I/O | Multiplexed I/O & Peripheral Pin PD4 (General) |
| 87 | PD5 | I/O | Multiplexed I/O & Peripheral Pin PD5 (General) |
| 88 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 89 | PB3 | I/O | Multiplexed I/O & Peripheral Pin PB3 (General) |
| 90 | PB4 | I/O | Multiplexed I/O & Peripheral Pin PB4 (General) |
| 91 | PB5 | I/O | Multiplexed I/O & Peripheral Pin PB5 (General) |
| 92 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (General) |
| 93 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (General) |
| 94 | BOOT0 | I | Input-Only Pin BOOT0 (General) |
| 95 | PB8 | I/O | Multiplexed I/O & Peripheral Pin PB8 (General) |
| 96 | PB9 | I/O | Multiplexed I/O & Peripheral Pin PB9 (General) |
| 97 | VCAP | I/O | Multiplexed I/O & Peripheral Pin VCAP (General) |
| 98 | VSS | GND | Ground Reference Pin (VSS) |
| 99 | VDDLDO | Power | Power Supply Input (VDDLDO — 3.3V VDD (Max 4.0V)) |
| 100 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
PIN 1 PE2
I/OMultiplexed I/O & Peripheral Pin PE2 (UART, SPI)
Design note: Alt: TRACECLK , SAI1_CK1 , USART10_RX , SPI4_SCK , SAI1_MCLKA_ , SAI4_MCLKA_ , OCTOSPIM_P1IO2_ , SAI4_CK1 , ETH_MIITXD3_ , FMC_A23 , EVENTOUT
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 23 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LQFP-100(14x14) · 14.00×14.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (23 figures · Page 1/2)
Showing 1–12 of 23 uncropped original figures for STM32H735
P58 · p58_fig01EXACT PACKAGE
P247 · p247_fig01EXACT PACKAGE
P248 · p248_fig01EXACT PACKAGE
P1 · p01_fig01881×1119px
P2 · p02_fig01887×578px
P57 · p57_fig011557×1281px
P57 · p57_fig021546×1189px
P58 · p58_fig01P58
P64 · p64_fig011642×2171px
P115 · p115_fig011546×2148px
P115 · p115_fig01P115
P143 · p143_fig011546×500px
Page 1 / 2 (23 extracted figures)
Technical Specifications & Part Details (STM32H735VGT6)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:STM32H735VGT6 (LQFP-100(14x14)) is a 100-pin embedded microcontroller unit (mcu) featuring a 14.00 × 14.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.62 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, IrDA, DAC, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.62 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
550 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
30 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
14.00 × 14.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-100(14x14))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, IrDA, DAC, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol100 auto-grouped pins
IPC-7351B Land Pattern100 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — STM32H735 (4)
LQFP-100(14x14) · 100P
IPC-7351B
100P14.0×14.0×1.60mmP=0.5mm
STM32H735 (LQFP-100(14x14))
LQFP-144(20x20) · 144P
IPC-7351B
144P20.0×20.0×1.60mmP=0.5mm
STM32H735 (LQFP-144(20x20))
UFBGA-201(10x10) · 201P
IPC-7351B
201P10.0×10.0×0.50mmP=0.65mm
STM32H735 (UFBGA-201(10x10))
Mechanical Dimensions & Land Pattern (LQFP-100(14x14))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
14.00 × 14.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
100P / 100Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-100(14x14) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32H735VGT6 (LQFP-100(14x14))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32H735VGT6 (LQFP-100(14x14))?
Manufactured by ST, the STM32H735VGT6 is housed in a LQFP-100(14x14) package with 100 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.62 V to 3.6 V. Key pins include: 1 (PE2: Multiplexed I/O & Peripheral Pin PE2 (UART, SPI)), 2 (PE4: Multiplexed I/O & Peripheral Pin PE4 (SPI)), 3 (PE5: Multiplexed I/O & Peripheral Pin PE5 (SPI)), 4 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), 5 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 6 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)).
What are the IPC-7351B PCB Footprint dimensions for STM32H735VGT6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H735VGT6 (LQFP-100(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H735VGT6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H735VGT6 (ST, LQFP-100(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (100 pins) & STM32H735 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PE2 | Digital_IO | Signal terminal PE2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_SCK. Supported peripheral buses: UART, SPI. |
| 2 | PE4 | Digital_IO | Signal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_NSS. Supported peripheral buses: SPI. |
| 3 | PE5 | Digital_IO | Signal terminal PE5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MISO. Supported peripheral buses: SPI. |
| 4 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 5 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 6 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK. |
| 7 | PC14 - OSC32_IN | Digital_IO | Signal terminal PC14 - OSC32_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN. Supported peripheral buses: RTC/CLK. |
| 8 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 9 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 10 | VLXSMPS | Digital_IO | Signal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General. |
| 11 | VDDSMPS | Power_In | Primary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 12 | VFBSMPS | Digital_IO | Signal terminal VFBSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VFBSMPS. Supported peripheral buses: General. |
| 13 | PH0 - OSC_IN | Digital_IO | Signal terminal PH0 - OSC_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0 - OSC_IN. Supported peripheral buses: RTC/CLK. |
| 14 | PH1 - OSC_OUT | Digital_IO | Signal terminal PH1 - OSC_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC_OUT. Supported peripheral buses: RTC/CLK. |
| 15 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| 16 | PC0 | Digital_IO | Signal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC. |
| 17 | PC1 | Digital_IO | Signal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, I2C, ADC, RTC/CLK. |
| 18 | PC2_C | Digital_IO | Signal terminal PC2_C (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2_C. Supported peripheral buses: ADC. |
| 19 | PC3_C | Digital_IO | Signal terminal PC3_C (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3_C. Supported peripheral buses: ADC. |
| 20 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 21 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 22 | VSSA | GND | 0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks. |
| 23 | VREF+ | Analog | Signal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General. |
| 24 | VDDA | Power_In | Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 25 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI6_NSS. Supported peripheral buses: UART, SPI, ADC, PWM. |
| 26 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM. |
| 27 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, SPI, ADC, PWM. |
| 28 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM. |
| 29 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 30 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 31 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS, SPI6_NSS. Supported peripheral buses: UART, SPI, ADC, DAC. |
| 32 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK, SPI6_SCK. Supported peripheral buses: SPI, ADC, DAC, PWM. |
| 33 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, SPI6_MISO. Supported peripheral buses: SPI, ADC, PWM. |
| 34 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI, SPI6_MOSI. Supported peripheral buses: SPI, ADC, PWM. |
| 35 | PC4 | Digital_IO | Signal terminal PC4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: UART, ADC. |
| 36 | PC5 | Digital_IO | Signal terminal PC5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: UART, ADC. |
| 37 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: UART, ADC, PWM. |
| 38 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM. |
| 39 | PB2 | Digital_IO | Signal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: SPI, I2C, RTC/CLK. |
| 40 | PE7 | Digital_IO | Signal terminal PE7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE7. Supported peripheral buses: UART. |
| 41 | PE8 | Digital_IO | Signal terminal PE8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE8. Supported peripheral buses: UART, PWM. |
| 42 | PB10 | Digital_IO | Signal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SCL, SPI2_SCK. Supported peripheral buses: UART, SPI, I2C, PWM. |
| 43 | PB11 | Digital_IO | Signal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: UART, I2C, PWM. |
| 44 | VCAP | Digital_IO | Signal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General. |
| 45 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 46 | VDDLDO | Power_In | Primary positive power supply input (VDDLDO) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 47 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 48 | PB12 | Digital_IO | Signal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SMBA, SPI2_NSS. Supported peripheral buses: UART, SPI, I2C. |
| 49 | PB13 | Digital_IO | Signal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, PWM. |
| 50 | PB14 | Digital_IO | Signal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI, PWM. |
| 51 | PB15 | Digital_IO | Signal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: UART, SPI, PWM, RTC/CLK. |
| 52 | PD8 | Digital_IO | Signal terminal PD8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD8. Supported peripheral buses: UART. |
| 53 | PD9 | Digital_IO | Signal terminal PD9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD9. Supported peripheral buses: UART. |
| 54 | PD10 | Digital_IO | Signal terminal PD10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD10. Supported peripheral buses: UART. |
| 55 | PD11 | Digital_IO | Signal terminal PD11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C4_SMBA. Supported peripheral buses: UART, SPI, I2C. |
| 56 | PD12 | Digital_IO | Signal terminal PD12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C4_SCL. Supported peripheral buses: UART, I2C, PWM. |
| 57 | PD13 | Digital_IO | Signal terminal PD13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C4_SDA. Supported peripheral buses: UART, SPI, I2C, PWM. |
| 58 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 59 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 60 | PD14 | Digital_IO | Signal terminal PD14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: UART, PWM. |
| 61 | PD15 | Digital_IO | Signal terminal PD15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: UART, PWM. |
| 62 | PC6 | Digital_IO | Signal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General. |
| 63 | PC7 | Digital_IO | Signal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General. |
| 64 | PC8 | Digital_IO | Signal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General. |