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STM32H735RGV6 (VFQFPN-68(8x8)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32H735RGV6

STID: C5271173VFQFPN-68(8x8) · 69 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32H735RGV6 (VFQFPN-68(8x8))1VBAT2PC14 - OSC323PC15 - OSC324VSSSMPS5VLXSMPS6VDDSMPS7VFBSMPS8VSS9VDD10PH0 - OSC_IN11PH1 - OSC_OU12NRST13PC014PC115VSSA16VDDA17PA018PA119PA220PA321VSS22VDD23PA424PA525PA626PA727PC428PC529PB030PB131PB232PB1033VCAP34VSS35VDD69VSS68VDD67VSS66VCAP65PE1564PE1463PE1362PE1261PD1560PD1459VDD58VSS57PD1356PD1255PD1154PD1053PD952PA1451VDD50VSS49VCAP48PA1347PA1246PA1145PA1044PA943PA842PC941PE840PE739PB1538PB1437PB1336PB12Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.850.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869E=8.00mm · Pitch e=0.40mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (69/69)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
2PC14 - OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (RTC/CLK)
3PC15 - OSC32_ OUTI/OMultiplexed I/O & Peripheral Pin PC15 - OSC32_ OUT (RTC/CLK)
4VSSSMPSGNDGround Reference Pin (VSSSMPS)
5VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
6VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
7VFBSMPSI/OMultiplexed I/O & Peripheral Pin VFBSMPS (General)
8VSSGNDGround Reference Pin (VSS)
9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
10PH0 - OSC_INI/OMultiplexed I/O & Peripheral Pin PH0 - OSC_IN (RTC/CLK)
11PH1 - OSC_OUTI/OMultiplexed I/O & Peripheral Pin PH1 - OSC_OUT (RTC/CLK)
12NRSTISystem Enable & Hardware Reset (NRST)
13PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
14PC1I/OMultiplexed I/O & Peripheral Pin PC1 (SPI, I2C, ADC, RTC/CLK)
15VSSAGNDGround Reference Pin (VSSA)
16VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
17PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, SPI, ADC, PWM)
18PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
19PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, SPI, ADC, PWM)
20PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
21VSSGNDGround Reference Pin (VSS)
22VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
23PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
24PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM)
25PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
26PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
27PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART, ADC)
28PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART, ADC)
29PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, ADC, PWM)
30PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
31PB2I/OMultiplexed I/O & Peripheral Pin PB2 (SPI, I2C, RTC/CLK)
32PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, SPI, I2C, PWM)
33VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
34VSSGNDGround Reference Pin (VSS)
35VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
36PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)
37PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
38PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
39PB15I/OMultiplexed I/O & Peripheral Pin PB15 (UART, SPI, PWM, RTC/CLK)
40PE7I/OMultiplexed I/O & Peripheral Pin PE7 (UART)
41PE8I/OMultiplexed I/O & Peripheral Pin PE8 (UART, PWM)
42PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
43PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
44PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
45PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
46PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
47PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
48PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
49VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
50VSSGNDGround Reference Pin (VSS)
51VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
52PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
53PD9I/OMultiplexed I/O & Peripheral Pin PD9 (UART)
54PD10I/OMultiplexed I/O & Peripheral Pin PD10 (UART)
55PD11I/OMultiplexed I/O & Peripheral Pin PD11 (UART, SPI, I2C)
56PD12I/OMultiplexed I/O & Peripheral Pin PD12 (UART, I2C, PWM)
57PD13I/OMultiplexed I/O & Peripheral Pin PD13 (UART, SPI, PWM)
58VSSGNDGround Reference Pin (VSS)
59VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
60PD14I/OMultiplexed I/O & Peripheral Pin PD14 (UART, PWM)
61PD15I/OMultiplexed I/O & Peripheral Pin PD15 (UART, PWM)
62PE12I/OMultiplexed I/O & Peripheral Pin PE12 (SPI, PWM)
63PE13I/OMultiplexed I/O & Peripheral Pin PE13 (SPI, PWM)
64PE14I/OMultiplexed I/O & Peripheral Pin PE14 (SPI, PWM)
65PE15I/OMultiplexed I/O & Peripheral Pin PE15 (UART)
66VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
67VSSGNDGround Reference Pin (VSS)
68VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
69VSSGNDGround Reference Pin (VSS)
PIN 1 VBAT
Power
Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32H735RGV6 (ST · VFQFPN-68(8x8))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32H735RGV6 (VFQFPN-68(8x8)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32H735RGV6 (VFQFPN-68(8x8)) - 2. Standard Pinout (Top View)
True package pinout (69 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32H735RGV6 (VFQFPN-68(8x8)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32H735RGV6 (VFQFPN-68(8x8)) - 4. Package Dimensions (D×E×A)
VFQFPN-68(8x8) · 8.00×8.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32H735RGV6 (VFQFPN-68(8x8)) - 5. Recommended Land Pattern
IPC-7351B Footprint (69 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32H735RGV6 (VFQFPN-68(8x8)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for STM32H735
P57 · p57_fig01EXACT PACKAGE
STM32H735RGV6 (VFQFPN-68(8x8)) — Figure 4. VFQFPN68 pinout
Figure 4. VFQFPN68 pinout
P252 · p252_fig01EXACT PACKAGE
STM32H735RGV6 (VFQFPN-68(8x8)) — Figure 72. VFQFPN68 - Outline D
Figure 72. VFQFPN68 - Outline D
P253 · p253_fig01EXACT PACKAGE
STM32H735RGV6 (VFQFPN-68(8x8)) — Figure 73. VFQFPN68 - Recommended footprint
Figure 73. VFQFPN68 - Recommended footprint
P1 · p01_fig01881×1115px
STM32H735RGV6 (VFQFPN-68(8x8)) — • POR, PDR, PVD and BOR
• POR, PDR, PVD and BOR
P57 · p57_fig021546×1068px
STM32H735RGV6 (VFQFPN-68(8x8)) — Figure 5. TFBGA100 pinout
Figure 5. TFBGA100 pinout
P57 · p57_fig01P57
STM32H735RGV6 (VFQFPN-68(8x8)) — Datasheet Page 57 (p57_fig01)
Datasheet Page 57 (p57_fig01)
P58 · p58_fig011553×1548px
STM32H735RGV6 (VFQFPN-68(8x8)) — Figure 6. LQFP100 pinout
Figure 6. LQFP100 pinout
P60 · p60_fig011751×1679px
STM32H735RGV6 (VFQFPN-68(8x8)) — Figure 8. LQFP144 pinout
Figure 8. LQFP144 pinout
P114 · p114_fig011546×2148px
STM32H735RGV6 (VFQFPN-68(8x8)) — Figure 14. Power supply scheme
Figure 14. Power supply scheme
P114 · p114_fig01P114
STM32H735RGV6 (VFQFPN-68(8x8)) — Datasheet Page 114 (p114_fig01)
Datasheet Page 114 (p114_fig01)
P149 · p149_fig011546×500px
STM32H735RGV6 (VFQFPN-68(8x8)) — Figure 24. Typical application with an 8 MHz crystal
Figure 24. Typical application with an 8 MHz crystal
P150 · p150_fig011546×516px
STM32H735RGV6 (VFQFPN-68(8x8)) — Figure 25. Typical application with a 32.768 kHz crystal
Figure 25. Typical application with a 32.768 kHz crystal
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (STM32H735RGV6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32H735RGV6 (VFQFPN-68(8x8)) is a 68-pin embedded microcontroller unit (mcu) featuring a 8.00 × 8.00 × 0.90 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.62 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, IrDA, DAC, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.62 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
550 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
29 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 0.90 mm (A1=0.04 mm)
Package family: QFN (VFQFPN-68(8x8))
Pin Count & Lead PitchN / e
68 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, IrDA, DAC, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol69 auto-grouped pins
OK
IPC-7351B Land Pattern69 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 6.40×6.40mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (VFQFPN-68(8x8))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.40mm
Pad Size (W × L)Level B
0.25 × 0.65 mm
Pins / Total PadsTopology
69P / 69Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
VFQFPN-68(8x8)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32H735RGV6 (VFQFPN-68(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32H735RGV6 (VFQFPN-68(8x8))?

Manufactured by ST, the STM32H735RGV6 is housed in a VFQFPN-68(8x8) package with 69 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.62 V to 3.6 V. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC14 - OSC32_IN: Multiplexed I/O & Peripheral Pin PC14 - OSC32_IN (RTC/CLK)), 3 (PC15 - OSC32_ OUT: Multiplexed I/O & Peripheral Pin PC15 - OSC32_ OUT (RTC/CLK)), 4 (VSSSMPS: Ground Reference Pin (VSSSMPS)), 5 (VLXSMPS: Multiplexed I/O & Peripheral Pin VLXSMPS (General)), 6 (VDDSMPS: Power Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))).

What are the IPC-7351B PCB Footprint dimensions for STM32H735RGV6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H735RGV6 (VFQFPN-68(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.40 mm, and 69 copper pads plus a central exposed thermal pad (EPAD) of 6.40 × 6.40 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H735RGV6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H735RGV6 (ST, VFQFPN-68(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (69 pins) & STM32H735 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
2PC14 - OSC32_INDigital_IOSignal terminal PC14 - OSC32_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN. Supported peripheral buses: RTC/CLK.
3PC15 - OSC32_ OUTDigital_IOSignal terminal PC15 - OSC32_ OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15 - OSC32_ OUT. Supported peripheral buses: RTC/CLK.
4VSSSMPSGND0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
5VLXSMPSDigital_IOSignal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General.
6VDDSMPSPower_InPrimary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
7VFBSMPSDigital_IOSignal terminal VFBSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VFBSMPS. Supported peripheral buses: General.
8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
9VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
10PH0 - OSC_INDigital_IOSignal terminal PH0 - OSC_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0 - OSC_IN. Supported peripheral buses: RTC/CLK.
11PH1 - OSC_OUTDigital_IOSignal terminal PH1 - OSC_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC_OUT. Supported peripheral buses: RTC/CLK.
12NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
13PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
14PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, I2C, ADC, RTC/CLK.
15VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
16VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
17PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI6_NSS. Supported peripheral buses: UART, SPI, ADC, PWM.
18PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
19PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, SPI, ADC, PWM.
20PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
21VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
22VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
23PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS, SPI6_NSS. Supported peripheral buses: UART, SPI, ADC, DAC.
24PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK, SPI6_SCK. Supported peripheral buses: SPI, ADC, DAC, PWM.
25PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, SPI6_MISO. Supported peripheral buses: SPI, ADC, PWM.
26PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI, SPI6_MOSI. Supported peripheral buses: SPI, ADC, PWM.
27PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: UART, ADC.
28PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: UART, ADC.
29PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: UART, ADC, PWM.
30PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM.
31PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: SPI, I2C, RTC/CLK.
32PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SCL, SPI2_SCK. Supported peripheral buses: UART, SPI, I2C, PWM.
33VCAPDigital_IOSignal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
34VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
35VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
36PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SMBA, SPI2_NSS. Supported peripheral buses: UART, SPI, I2C.
37PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, PWM.
38PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI, PWM.
39PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: UART, SPI, PWM, RTC/CLK.
40PE7Digital_IOSignal terminal PE7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE7. Supported peripheral buses: UART.
41PE8Digital_IOSignal terminal PE8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE8. Supported peripheral buses: UART, PWM.
42PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
43PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
44PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
45PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
46PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
47PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
48PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
49VCAPDigital_IOSignal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
50VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
51VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
52PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
53PD9Digital_IOSignal terminal PD9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD9. Supported peripheral buses: UART.
54PD10Digital_IOSignal terminal PD10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD10. Supported peripheral buses: UART.
55PD11Digital_IOSignal terminal PD11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C4_SMBA. Supported peripheral buses: UART, SPI, I2C.
56PD12Digital_IOSignal terminal PD12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C4_SCL. Supported peripheral buses: UART, I2C, PWM.
57PD13Digital_IOSignal terminal PD13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: UART, SPI, PWM.
58VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
59VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
60PD14Digital_IOSignal terminal PD14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: UART, PWM.
61PD15Digital_IOSignal terminal PD15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: UART, PWM.
62PE12Digital_IOSignal terminal PE12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_SCK. Supported peripheral buses: SPI, PWM.
63PE13Digital_IOSignal terminal PE13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MISO. Supported peripheral buses: SPI, PWM.
64PE14Digital_IOSignal terminal PE14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MOSI. Supported peripheral buses: SPI, PWM.
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