ChipDocs.org
⌘K
2284 PARTSUpload PDF
USB2503A-HZH (QFN-48-EP(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

USB2503A-HZH

MICROCHIPID: C633593QFN-48-EP(7x7) · 49 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · USB2503A-HZH (QFN-48-EP(7x7))1VDDA332USBDP03COMPOUND4MTT_ENABLE5HS_DISABLE6Reserved7VDDA338USBDP29USBDN210VSS11USBDN312USBDP313VDDA3314PRTPWER315OCS3_N16PRTPWR217GR3/PRT_DIS018PRTPWR_POL19GR2/NON_REM120GANG_EN21GR1/NON_REM022VSS23VDD1824TEST025SDA/SMBDATA49EP48VSS47RBIAS46ATEST/REG_EN45VDDA33PLL44VDDA18PLL43XTAL1/CLKIN42XTAL241VSS40VDD1839VDD33CR38VSS37RESET_N36TEST135CLKIN_EN34OCS1_N33PRTPWR132OCS2_N31VDD1830VSS29VBUS_DET28SELF_PWR27CFG_SEL126SCL/SMBCLK/CGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.838.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849E=7.00mm · Pitch e=0.50mmD=7.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDDA33PowerPower Supply Input (VDDA33 — 3.3V / 5.0V Standard Logic)
2USBDP0I/OMultiplexed I/O & Peripheral Pin USBDP0 (USB)
3COMPOUNDI/OMultiplexed I/O & Peripheral Pin COMPOUND (General)
4MTT_ENABLEI/OMultiplexed I/O & Peripheral Pin MTT_ENABLE (General)
5HS_DISABLEI/OMultiplexed I/O & Peripheral Pin HS_DISABLE (General)
6ReservedI/OMultiplexed I/O & Peripheral Pin Reserved (General)
7VDDA33PowerPower Supply Input (VDDA33 — 3.3V / 5.0V Standard Logic)
8USBDP2I/OMultiplexed I/O & Peripheral Pin USBDP2 (USB)
9USBDN2I/OMultiplexed I/O & Peripheral Pin USBDN2 (USB)
10VSSGNDGround Reference Pin (VSS)
11USBDN3I/OMultiplexed I/O & Peripheral Pin USBDN3 (USB)
12USBDP3I/OMultiplexed I/O & Peripheral Pin USBDP3 (USB)
13VDDA33PowerPower Supply Input (VDDA33 — 3.3V / 5.0V Standard Logic)
14PRTPWER3I/OMultiplexed I/O & Peripheral Pin PRTPWER3 (General)
15OCS3_NI/OMultiplexed I/O & Peripheral Pin OCS3_N (General)
16PRTPWR2I/OMultiplexed I/O & Peripheral Pin PRTPWR2 (General)
17GR3/PRT_DIS0I/OMultiplexed I/O & Peripheral Pin GR3/PRT_DIS0 (General)
18PRTPWR_POLI/OMultiplexed I/O & Peripheral Pin PRTPWR_POL (General)
19GR2/NON_REM1I/OMultiplexed I/O & Peripheral Pin GR2/NON_REM1 (General)
20GANG_ENI/OMultiplexed I/O & Peripheral Pin GANG_EN (General)
21GR1/NON_REM0I/OMultiplexed I/O & Peripheral Pin GR1/NON_REM0 (General)
22VSSGNDGround Reference Pin (VSS)
23VDD18PowerPower Supply Input (VDD18 — 3.3V / 5.0V Standard Logic)
24TEST0I/OMultiplexed I/O & Peripheral Pin TEST0 (General)
25SDA/SMBDATAI/OMultiplexed I/O & Peripheral Pin SDA/SMBDATA (I2C)
26SCL/SMBCLK/CFG_SEL0I/OMultiplexed I/O & Peripheral Pin SCL/SMBCLK/CFG_SEL0 (I2C)
27CFG_SEL1I/OMultiplexed I/O & Peripheral Pin CFG_SEL1 (General)
28SELF_PWRI/OMultiplexed I/O & Peripheral Pin SELF_PWR (General)
29VBUS_DETPowerPower Supply Input (VBUS_DET — 3.3V / 5.0V Standard Logic)
30VSSGNDGround Reference Pin (VSS)
31VDD18PowerPower Supply Input (VDD18 — 3.3V / 5.0V Standard Logic)
32OCS2_NI/OMultiplexed I/O & Peripheral Pin OCS2_N (General)
33PRTPWR1I/OMultiplexed I/O & Peripheral Pin PRTPWR1 (General)
34OCS1_NI/OMultiplexed I/O & Peripheral Pin OCS1_N (General)
35CLKIN_ENI/OMultiplexed I/O & Peripheral Pin CLKIN_EN (General)
36TEST1I/OMultiplexed I/O & Peripheral Pin TEST1 (General)
37RESET_NISystem Enable & Hardware Reset (RESET_N)
38VSSGNDGround Reference Pin (VSS)
39VDD33CRPowerPower Supply Input (VDD33CR — 3.3V / 5.0V Standard Logic)
40VDD18PowerPower Supply Input (VDD18 — 3.3V / 5.0V Standard Logic)
41VSSGNDGround Reference Pin (VSS)
42XTAL2I/OMultiplexed I/O & Peripheral Pin XTAL2 (RTC/CLK)
43XTAL1/CLKINI/OMultiplexed I/O & Peripheral Pin XTAL1/CLKIN (RTC/CLK)
44VDDA18PLLPowerPower Supply Input (VDDA18PLL — 3.3V / 5.0V Standard Logic)
45VDDA33PLLPowerPower Supply Input (VDDA33PLL — 3.3V / 5.0V Standard Logic)
46ATEST/REG_ENI/OMultiplexed I/O & Peripheral Pin ATEST/REG_EN (General)
47RBIASI/OMultiplexed I/O & Peripheral Pin RBIAS (General)
48VSSGNDGround Reference Pin (VSS)
49EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 VDDA33
Power
Power Supply Input (VDDA33 — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VDDA33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: USB2503A-HZH (MICROCHIP · QFN-48-EP(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
USB2503A-HZH (QFN-48-EP(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
USB2503A-HZH (QFN-48-EP(7x7)) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
USB2503A-HZH (QFN-48-EP(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
USB2503A-HZH (QFN-48-EP(7x7)) - 4. Package Dimensions (D×E×A)
QFN-48-EP(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
USB2503A-HZH (QFN-48-EP(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
USB2503A-HZH (QFN-48-EP(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for USB2503
P6 · p06_fig01EXACT PACKAGE
USB2503A-HZH (QFN-48-EP(7x7)) — FIGURE 3-1: 3-PORT 48-PIN QFN
FIGURE 3-1: 3-PORT 48-PIN QFN
P1 · p01_fig01377×200px
USB2503A-HZH (QFN-48-EP(7x7)) — Integrated USB 2.0 Compatible 3-Port Hub
Integrated USB 2.0 Compatible 3-Port Hub
P6 · p06_fig01P6
USB2503A-HZH (QFN-48-EP(7x7)) — Datasheet Page 6 (p06_fig01)
Datasheet Page 6 (p06_fig01)
P35 · p35_fig011777×2303px
USB2503A-HZH (QFN-48-EP(7x7)) — FIGURE 9-1: 48-PIN QFN PACKAGE OUTLINE (7X7MM BODY - 0.5MM PITCH)
FIGURE 9-1: 48-PIN QFN PACKAGE OUTLINE (7X7MM BODY - 0.5MM PITCH)
P36 · p36_fig011777×2438px
USB2503A-HZH (QFN-48-EP(7x7)) — FIGURE 9-1: 48-PIN QFN PACKAGE OUTLINE (7X7MM BODY - 0.5MM PITCH) (CONTINUED)
FIGURE 9-1: 48-PIN QFN PACKAGE OUTLINE (7X7MM BODY - 0.5MM PITCH) (CONTINUED)

Technical Specifications & Part Details (USB2503A-HZH)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:USB2503A-HZH (QFN-48-EP(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, I2C, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
24MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-48-EP(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, I2C, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 5.30×5.30mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-48-EP(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.85 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-48-EP(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — USB2503A-HZH (QFN-48-EP(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of USB2503A-HZH (QFN-48-EP(7x7))?

Manufactured by MICROCHIP, the USB2503A-HZH is housed in a QFN-48-EP(7x7) package with 49 pins and a 0.50 mm lead pitch. Key pins include: 1 (VDDA33: Power Supply Input (VDDA33 — 3.3V / 5.0V Standard Logic)), 2 (USBDP0: Multiplexed I/O & Peripheral Pin USBDP0 (USB)), 3 (COMPOUND: Multiplexed I/O & Peripheral Pin COMPOUND (General)), 4 (MTT_ENABLE: Multiplexed I/O & Peripheral Pin MTT_ENABLE (General)), 5 (HS_DISABLE: Multiplexed I/O & Peripheral Pin HS_DISABLE (General)), 6 (Reserved: Multiplexed I/O & Peripheral Pin Reserved (General)).

What are the IPC-7351B PCB Footprint dimensions for USB2503A-HZH?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), USB2503A-HZH (QFN-48-EP(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 5.30 × 5.30 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for USB2503A-HZH?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for USB2503A-HZH (MICROCHIP, QFN-48-EP(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & USB2503 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDDA33Power_InPrimary positive power supply input (VDDA33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2USBDP0Digital_IOSignal terminal USBDP0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USBDP0. Supported peripheral buses: USB.
3COMPOUNDDigital_IOSignal terminal COMPOUND (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: COMPOUND. Supported peripheral buses: General.
4MTT_ENABLEDigital_IOSignal terminal MTT_ENABLE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MTT_ENABLE. Supported peripheral buses: General.
5HS_DISABLEDigital_IOSignal terminal HS_DISABLE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HS_DISABLE. Supported peripheral buses: General.
6ReservedDigital_IOSignal terminal Reserved (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Reserved. Supported peripheral buses: General.
7VDDA33Power_InPrimary positive power supply input (VDDA33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
8USBDP2Digital_IOSignal terminal USBDP2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USBDP2. Supported peripheral buses: USB.
9USBDN2Digital_IOSignal terminal USBDN2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USBDN2. Supported peripheral buses: USB.
10VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
11USBDN3Digital_IOSignal terminal USBDN3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USBDN3. Supported peripheral buses: USB.
12USBDP3Digital_IOSignal terminal USBDP3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USBDP3. Supported peripheral buses: USB.
13VDDA33Power_InPrimary positive power supply input (VDDA33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
14PRTPWER3Digital_IOSignal terminal PRTPWER3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PRTPWER3. Supported peripheral buses: General.
15OCS3_NDigital_IOSignal terminal OCS3_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OCS3_N. Supported peripheral buses: General.
16PRTPWR2Digital_IOSignal terminal PRTPWR2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PRTPWR2. Supported peripheral buses: General.
17GR3/PRT_DIS0Digital_IOSignal terminal GR3/PRT_DIS0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GR3/PRT_DIS0. Supported peripheral buses: General.
18PRTPWR_POLDigital_IOSignal terminal PRTPWR_POL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PRTPWR_POL. Supported peripheral buses: General.
19GR2/NON_REM1Digital_IOSignal terminal GR2/NON_REM1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GR2/NON_REM1. Supported peripheral buses: General.
20GANG_ENDigital_IOSignal terminal GANG_EN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GANG_EN. Supported peripheral buses: General.
21GR1/NON_REM0Digital_IOSignal terminal GR1/NON_REM0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GR1/NON_REM0. Supported peripheral buses: General.
22VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
23VDD18Power_InPrimary positive power supply input (VDD18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
24TEST0Digital_IOSignal terminal TEST0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TEST0. Supported peripheral buses: General.
25SDA/SMBDATADigital_IOSignal terminal SDA/SMBDATA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA/SMBDATA. Supported peripheral buses: I2C.
26SCL/SMBCLK/CFG_SEL0Digital_IOSignal terminal SCL/SMBCLK/CFG_SEL0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL/SMBCLK/CFG_SEL0. Supported peripheral buses: I2C.
27CFG_SEL1Digital_IOSignal terminal CFG_SEL1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG_SEL1. Supported peripheral buses: General.
28SELF_PWRDigital_IOSignal terminal SELF_PWR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SELF_PWR. Supported peripheral buses: General.
29VBUS_DETPower_InPrimary positive power supply input (VBUS_DET) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
30VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
31VDD18Power_InPrimary positive power supply input (VDD18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
32OCS2_NDigital_IOSignal terminal OCS2_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OCS2_N. Supported peripheral buses: General.
33PRTPWR1Digital_IOSignal terminal PRTPWR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PRTPWR1. Supported peripheral buses: General.
34OCS1_NDigital_IOSignal terminal OCS1_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OCS1_N. Supported peripheral buses: General.
35CLKIN_ENDigital_IOSignal terminal CLKIN_EN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLKIN_EN. Supported peripheral buses: General.
36TEST1Digital_IOSignal terminal TEST1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TEST1. Supported peripheral buses: General.
37RESET_NDigital_IOActive-low hardware reset terminal (RESET_N): pulling this pin Low resets the processor core and peripherals.
38VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
39VDD33CRPower_InPrimary positive power supply input (VDD33CR) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
40VDD18Power_InPrimary positive power supply input (VDD18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
41VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
42XTAL2Digital_IOSignal terminal XTAL2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XTAL2. Supported peripheral buses: RTC/CLK.
43XTAL1/CLKINDigital_IOSignal terminal XTAL1/CLKIN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XTAL1/CLKIN. Supported peripheral buses: RTC/CLK.
44VDDA18PLLPower_InPrimary positive power supply input (VDDA18PLL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
45VDDA33PLLPower_InPrimary positive power supply input (VDDA33PLL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
46ATEST/REG_ENDigital_IOSignal terminal ATEST/REG_EN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ATEST/REG_EN. Supported peripheral buses: General.
47RBIASDigital_IOSignal terminal RBIAS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RBIAS. Supported peripheral buses: General.
48VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
49EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
ExplorePartsPackagesMFRsUpload