ChipDocs.org
⌘K
2284 PARTSUpload PDF
LAN8820-ABZJ-TR (QFN-56-EP(8x8)) — Symbol, Footprint IPC-7351B & 3D STEP Model

LAN8820-ABZJ-TR

MICROCHIPID: C625088QFN-56-EP(8x8) · 57 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · LAN8820-ABZJ-TR (QFN-56-EP(8x8))1No Connect2TCK3TMS4NC5XI6IO37VDD25IO8VDD12CORE9RXD010RXD111RXD212RXD313VDD12CORE14RXCTRL15HPD16nRESET17IRQ18RXC19VDD25IO20VDD12CORE21NC22TXD323VDD12CORE24VDD25IO25TXD226TXD127TXD028TXCTRL29TXC57EP56VDD12A55TR3P54TR3N53VDD12A52TR2P51TR2N50VDD12PLL49VDD12BIAS48VDD12A47TR1P46TR1N45VDD12A44TR0P43TR0N42ETHRBIAS41MDIO40MDC39CONFIG038CONFIG137VDD25IO36VDD12CORE35CONFIG234CONFIG33310_LED#32100_LED/HPD_31IO3130VDD12COREGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.843.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657E=8.00mm · Pitch e=0.50mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (57/57)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1No ConnectI/OMultiplexed I/O & Peripheral Pin No Connect (General)
2TCKI/OMultiplexed I/O & Peripheral Pin TCK (General)
3TMSI/OMultiplexed I/O & Peripheral Pin TMS (General)
4NCNCNo Connect (Leave Floating)
5XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
6IO3I/OGPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)
7VDD25IOPowerPower Supply Input (VDD25IO — 3.3V / 5.0V Standard Logic)
8VDD12COREPowerPower Supply Input (VDD12CORE — 3.3V / 5.0V Standard Logic)
9RXD0I/OMultiplexed I/O & Peripheral Pin RXD0 (UART)
10RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
11RXD2I/OMultiplexed I/O & Peripheral Pin RXD2 (UART)
12RXD3I/OMultiplexed I/O & Peripheral Pin RXD3 (UART)
13VDD12COREPowerPower Supply Input (VDD12CORE — 3.3V / 5.0V Standard Logic)
14RXCTRLI/OMultiplexed I/O & Peripheral Pin RXCTRL (General)
15HPDI/OMultiplexed I/O & Peripheral Pin HPD (General)
16nRESETISystem Enable & Hardware Reset (nRESET)
17IRQI/OMultiplexed I/O & Peripheral Pin IRQ (General)
18RXCI/OMultiplexed I/O & Peripheral Pin RXC (General)
19VDD25IOPowerPower Supply Input (VDD25IO — 3.3V / 5.0V Standard Logic)
20VDD12COREPowerPower Supply Input (VDD12CORE — 3.3V / 5.0V Standard Logic)
21NCI/OMultiplexed I/O & Peripheral Pin NC (General)
22TXD3I/OMultiplexed I/O & Peripheral Pin TXD3 (UART)
23VDD12COREPowerPower Supply Input (VDD12CORE — 3.3V / 5.0V Standard Logic)
24VDD25IOPowerPower Supply Input (VDD25IO — 3.3V / 5.0V Standard Logic)
25TXD2I/OMultiplexed I/O & Peripheral Pin TXD2 (UART)
26TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
27TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
28TXCTRLI/OMultiplexed I/O & Peripheral Pin TXCTRL (General)
29TXCI/OMultiplexed I/O & Peripheral Pin TXC (General)
30VDD12COREPowerPower Supply Input (VDD12CORE — 3.3V / 5.0V Standard Logic)
31IO31I/OGeneral Purpose Digital I/O Pin IO31
32100_LED/HPD_MODE#I/OMultiplexed I/O & Peripheral Pin 100_LED/HPD_MODE# (General)
3310_LED#I/OMultiplexed I/O & Peripheral Pin 10_LED# (General)
34CONFIG3I/OMultiplexed I/O & Peripheral Pin CONFIG3 (General)
35CONFIG2I/OMultiplexed I/O & Peripheral Pin CONFIG2 (General)
36VDD12COREPowerPower Supply Input (VDD12CORE — 3.3V / 5.0V Standard Logic)
37VDD25IOPowerPower Supply Input (VDD25IO — 3.3V / 5.0V Standard Logic)
38CONFIG1I/OMultiplexed I/O & Peripheral Pin CONFIG1 (General)
39CONFIG0I/OMultiplexed I/O & Peripheral Pin CONFIG0 (General)
40MDCI/OMultiplexed I/O & Peripheral Pin MDC (General)
41MDIOI/OMultiplexed I/O & Peripheral Pin MDIO (General)
42ETHRBIASI/OMultiplexed I/O & Peripheral Pin ETHRBIAS (General)
43TR0NI/OMultiplexed I/O & Peripheral Pin TR0N (General)
44TR0PI/OMultiplexed I/O & Peripheral Pin TR0P (General)
45VDD12APowerPower Supply Input (VDD12A — 3.3V / 5.0V Standard Logic)
46TR1NI/OMultiplexed I/O & Peripheral Pin TR1N (General)
47TR1PI/OMultiplexed I/O & Peripheral Pin TR1P (General)
48VDD12APowerPower Supply Input (VDD12A — 3.3V / 5.0V Standard Logic)
49VDD12BIASPowerPower Supply Input (VDD12BIAS — 3.3V / 5.0V Standard Logic)
50VDD12PLLPowerPower Supply Input (VDD12PLL — 3.3V / 5.0V Standard Logic)
51TR2NI/OMultiplexed I/O & Peripheral Pin TR2N (General)
52TR2PI/OMultiplexed I/O & Peripheral Pin TR2P (General)
53VDD12APowerPower Supply Input (VDD12A — 3.3V / 5.0V Standard Logic)
54TR3NI/OMultiplexed I/O & Peripheral Pin TR3N (General)
55TR3PI/OMultiplexed I/O & Peripheral Pin TR3P (General)
56VDD12APowerPower Supply Input (VDD12A — 3.3V / 5.0V Standard Logic)
57EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 No Connect
I/O
Multiplexed I/O & Peripheral Pin No Connect (General)
Design note: This pin must be left floating for normal device oper atio n .
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: LAN8820-ABZJ-TR (MICROCHIP · QFN-56-EP(8x8))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
LAN8820-ABZJ-TR (QFN-56-EP(8x8)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
LAN8820-ABZJ-TR (QFN-56-EP(8x8)) - 2. Standard Pinout (Top View)
True package pinout (57 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
LAN8820-ABZJ-TR (QFN-56-EP(8x8)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LAN8820-ABZJ-TR (QFN-56-EP(8x8)) - 4. Package Dimensions (D×E×A)
QFN-56-EP(8x8) · 8.00×8.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
LAN8820-ABZJ-TR (QFN-56-EP(8x8)) - 5. Recommended Land Pattern
IPC-7351B Footprint (57 Pads)Expand ›
6. Application SchematicSCHEMATIC
LAN8820-ABZJ-TR (QFN-56-EP(8x8)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for LAN8820
P1 · p01_fig01376×200px
LAN8820-ABZJ-TR (QFN-56-EP(8x8)) — RGMII 10/100/1000 Ethernet Transceiver
RGMII 10/100/1000 Ethernet Transceiver
P5 · p05_fig011698×1761px
LAN8820-ABZJ-TR (QFN-56-EP(8x8)) — FIGURE 2-1: 56-QFN PIN ASSIGNMENTS (TOP VIEW)
FIGURE 2-1: 56-QFN PIN ASSIGNMENTS (TOP VIEW)
P5 · p05_fig01P5
LAN8820-ABZJ-TR (QFN-56-EP(8x8)) — Datasheet Page 5 (p05_fig01)
Datasheet Page 5 (p05_fig01)
P76 · p76_fig011778×2105px
LAN8820-ABZJ-TR (QFN-56-EP(8x8)) — FIGURE 6-1: 56-QFN PACKAGE
FIGURE 6-1: 56-QFN PACKAGE
P76 · p76_fig021532×1185px
LAN8820-ABZJ-TR (QFN-56-EP(8x8)) — FIGURE 6-1: 56-QFN PACKAGE
FIGURE 6-1: 56-QFN PACKAGE
P76 · p76_fig02P76
LAN8820-ABZJ-TR (QFN-56-EP(8x8)) — Datasheet Page 76 (p76_fig02)
Datasheet Page 76 (p76_fig02)
P77 · p77_fig011382×1191px
LAN8820-ABZJ-TR (QFN-56-EP(8x8)) — FIGURE 6-2: 56-QFN RECOMMENDED PCB LAND PATTERN
FIGURE 6-2: 56-QFN RECOMMENDED PCB LAND PATTERN
P77 · p77_fig01P77
LAN8820-ABZJ-TR (QFN-56-EP(8x8)) — Datasheet Page 77 (p77_fig01)
Datasheet Page 77 (p77_fig01)
P79 · p79_fig011778×2287px
LAN8820-ABZJ-TR (QFN-56-EP(8x8)) — Revision Level & Date Section/Figure/Entry Correction
Revision Level & Date Section/Figure/Entry Correction

Technical Specifications & Part Details (LAN8820-ABZJ-TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:LAN8820-ABZJ-TR (QFN-56-EP(8x8)) is a 56-pin standard electronic & interconnect component featuring a 8.00 × 8.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across 0°C to +70°C with integrated JTAG / SWD, RTC/CLK, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
0°C to +70°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
25MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 0.85 mm (A1=0.04 mm)
Package family: QFN (QFN-56-EP(8x8))
Pin Count & Lead PitchN / e
56 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
JTAG / SWD, RTC/CLK, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol57 auto-grouped pins
OK
IPC-7351B Land Pattern57 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 5.90×5.90mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — LAN8820 (3)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (QFN-56-EP(8x8))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.22 × 0.85 mm
Pins / Total PadsTopology
57P / 57Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-56-EP(8x8)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — LAN8820-ABZJ-TR (QFN-56-EP(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of LAN8820-ABZJ-TR (QFN-56-EP(8x8))?

Manufactured by MICROCHIP, the LAN8820-ABZJ-TR is housed in a QFN-56-EP(8x8) package with 57 pins and a 0.50 mm lead pitch. Key pins include: 1 (No Connect: Multiplexed I/O & Peripheral Pin No Connect (General)), 2 (TCK: Multiplexed I/O & Peripheral Pin TCK (General)), 3 (TMS: Multiplexed I/O & Peripheral Pin TMS (General)), 4 (NC: No Connect (Leave Floating)), 5 (XI: Multiplexed I/O & Peripheral Pin XI (RTC/CLK)), 6 (IO3: GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)).

What are the IPC-7351B PCB Footprint dimensions for LAN8820-ABZJ-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), LAN8820-ABZJ-TR (QFN-56-EP(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.50 mm, and 57 copper pads plus a central exposed thermal pad (EPAD) of 5.90 × 5.90 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for LAN8820-ABZJ-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for LAN8820-ABZJ-TR (MICROCHIP, QFN-56-EP(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (57 pins) & LAN8820 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1No ConnectDigital_IOSignal terminal No Connect (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: No Connect. Supported peripheral buses: General.
2TCKDigital_IOSignal terminal TCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TCK. Supported peripheral buses: General.
3TMSDigital_IOSignal terminal TMS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TMS. Supported peripheral buses: General.
4NCNo_ConnectNo Connect (Leave Floating)
5XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
6IO3Digital_IOGPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)
7VDD25IOPower_InPrimary positive power supply input (VDD25IO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
8VDD12COREPower_InPrimary positive power supply input (VDD12CORE) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
9RXD0Digital_IOSignal terminal RXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD0. Supported peripheral buses: UART.
10RXD1Digital_IOSignal terminal RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART.
11RXD2Digital_IOSignal terminal RXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD2. Supported peripheral buses: UART.
12RXD3Digital_IOSignal terminal RXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD3. Supported peripheral buses: UART.
13VDD12COREPower_InPrimary positive power supply input (VDD12CORE) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
14RXCTRLDigital_IOSignal terminal RXCTRL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXCTRL. Supported peripheral buses: General.
15HPDDigital_IOSignal terminal HPD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HPD. Supported peripheral buses: General.
16nRESETDigital_IOActive-low hardware reset terminal (nRESET): pulling this pin Low resets the processor core and peripherals.
17IRQDigital_IOSignal terminal IRQ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IRQ. Supported peripheral buses: General.
18RXCDigital_IOSignal terminal RXC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXC. Supported peripheral buses: General.
19VDD25IOPower_InPrimary positive power supply input (VDD25IO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
20VDD12COREPower_InPrimary positive power supply input (VDD12CORE) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
21NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
22TXD3Digital_IOSignal terminal TXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD3. Supported peripheral buses: UART.
23VDD12COREPower_InPrimary positive power supply input (VDD12CORE) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
24VDD25IOPower_InPrimary positive power supply input (VDD25IO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
25TXD2Digital_IOSignal terminal TXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD2. Supported peripheral buses: UART.
26TXD1Digital_IOSignal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
27TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
28TXCTRLDigital_IOSignal terminal TXCTRL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXCTRL. Supported peripheral buses: General.
29TXCDigital_IOSignal terminal TXC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXC. Supported peripheral buses: General.
30VDD12COREPower_InPrimary positive power supply input (VDD12CORE) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
31IO31Digital_IOGeneral Purpose Digital I/O Pin IO31
32100_LED/HPD_MODE#Digital_IOSignal terminal 100_LED/HPD_MODE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: 100_LED/HPD_MODE#. Supported peripheral buses: General.
3310_LED#Digital_IOSignal terminal 10_LED# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: 10_LED#. Supported peripheral buses: General.
34CONFIG3Digital_IOSignal terminal CONFIG3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CONFIG3. Supported peripheral buses: General.
35CONFIG2Digital_IOSignal terminal CONFIG2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CONFIG2. Supported peripheral buses: General.
36VDD12COREPower_InPrimary positive power supply input (VDD12CORE) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
37VDD25IOPower_InPrimary positive power supply input (VDD25IO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
38CONFIG1Digital_IOSignal terminal CONFIG1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CONFIG1. Supported peripheral buses: General.
39CONFIG0Digital_IOSignal terminal CONFIG0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CONFIG0. Supported peripheral buses: General.
40MDCDigital_IOSignal terminal MDC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDC. Supported peripheral buses: General.
41MDIODigital_IOSignal terminal MDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIO. Supported peripheral buses: General.
42ETHRBIASDigital_IOSignal terminal ETHRBIAS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ETHRBIAS. Supported peripheral buses: General.
43TR0NDigital_IOSignal terminal TR0N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TR0N. Supported peripheral buses: General.
44TR0PDigital_IOSignal terminal TR0P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TR0P. Supported peripheral buses: General.
45VDD12APower_InPrimary positive power supply input (VDD12A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
46TR1NDigital_IOSignal terminal TR1N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TR1N. Supported peripheral buses: General.
47TR1PDigital_IOSignal terminal TR1P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TR1P. Supported peripheral buses: General.
48VDD12APower_InPrimary positive power supply input (VDD12A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
49VDD12BIASPower_InPrimary positive power supply input (VDD12BIAS) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
50VDD12PLLPower_InPrimary positive power supply input (VDD12PLL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
51TR2NDigital_IOSignal terminal TR2N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TR2N. Supported peripheral buses: General.
52TR2PDigital_IOSignal terminal TR2P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TR2P. Supported peripheral buses: General.
53VDD12APower_InPrimary positive power supply input (VDD12A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
54TR3NDigital_IOSignal terminal TR3N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TR3N. Supported peripheral buses: General.
55TR3PDigital_IOSignal terminal TR3P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TR3P. Supported peripheral buses: General.
56VDD12APower_InPrimary positive power supply input (VDD12A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
57EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
ExplorePartsPackagesMFRsUpload