QFN26C(3x3) · 26P
Synchronized Pinout (Symbol / 2D / 3D) (26/26)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | PC4/A2 | I/O | Multiplexed I/O & Peripheral Pin PC4/A2 (General) |
| 2 | PC5/RST/T2C1/CP0 | I/O | Multiplexed I/O & Peripheral Pin PC5/RST/T2C1/CP0 (General) |
| 3 | VSS | GND | Ground Reference Pin (VSS) |
| 4 | PD2/T2C3/CP2/A3 | I/O | Multiplexed I/O & Peripheral Pin PD2/T2C3/CP2/A3 (General) |
| 5 | PD1/SWIO/T1C4/OP3 | I/O | Multiplexed I/O & Peripheral Pin PD1/SWIO/T1C4/OP3 (General) |
| 6 | PD3/OP2/A4 | I/O | Multiplexed I/O & Peripheral Pin PD3/OP2/A4 (General) |
| 7 | PD4/A7 | I/O | Multiplexed I/O & Peripheral Pin PD4/A7 (General) |
| 8 | PD5/CN1/A5 | I/O | Multiplexed I/O & Peripheral Pin PD5/CN1/A5 (General) |
| 9 | PD6/A6 | I/O | Multiplexed I/O & Peripheral Pin PD6/A6 (General) |
| 10 | PD7/OP1/A+ | I/O | Multiplexed I/O & Peripheral Pin PD7/OP1/A+ (General) |
| 11 | PA4/ON2/A- | I/O | Multiplexed I/O & Peripheral Pin PA4/ON2/A- (General) |
| 12 | PA5/OO1/AO | I/O | Multiplexed I/O & Peripheral Pin PA5/OO1/AO (General) |
| 13 | VDD | Power | Power Supply Input (VDD — 3.3V / 5.0V Standard Logic) |
| 14 | VHREG | I/O | Multiplexed I/O & Peripheral Pin VHREG (General) |
| 15 | VHV | I/O | Multiplexed I/O & Peripheral Pin VHV (General) |
| 16 | HO1(PA3/T1C1) | I/O | Multiplexed I/O & Peripheral Pin HO1(PA3/T1C1) (General) |
| 17 | LO1(PA0/T1C1N) | I/O | Multiplexed I/O & Peripheral Pin LO1(PA0/T1C1N) (General) |
| 18 | HO2(PB0/T1C2) | I/O | Multiplexed I/O & Peripheral Pin HO2(PB0/T1C2) (General) |
| 19 | LO2(PA2/T1C2N) | I/O | Multiplexed I/O & Peripheral Pin LO2(PA2/T1C2N) (General) |
| 20 | HO3(PB1/T1C3) | I/O | Multiplexed I/O & Peripheral Pin HO3(PB1/T1C3) (General) |
| 21 | LO3(PD0/T1C3N) | I/O | Multiplexed I/O & Peripheral Pin LO3(PD0/T1C3N) (General) |
| 22 | PB3/SWCK/T1BK/T2C2/CP1 | I/O | Multiplexed I/O & Peripheral Pin PB3/SWCK/T1BK/T2C2/CP1 (General) |
| 23 | PC0/TX_/CPO | I/O | Multiplexed I/O & Peripheral Pin PC0/TX_/CPO (General) |
| 24 | PC1 | I/O | Multiplexed I/O & Peripheral Pin PC1 (SPI, I2C) |
| 25 | PC2/CN0/SCL | I/O | Multiplexed I/O & Peripheral Pin PC2/CN0/SCL (I2C) |
| 26 | PA1/ON0/A1 | I/O | Multiplexed I/O & Peripheral Pin PA1/ON0/A1 (General) |
PIN 1 PC4/A2
I/OMultiplexed I/O & Peripheral Pin PC4/A2 (General)
Design note: Signal terminal PC4/A2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4/A2. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 11 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (26 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
QFN26C(3x3) · 3.00×3.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (26 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)
Showing 1–11 of 11 uncropped original figures for CH32M007
P2 · p02_fig012022×848px
P14 · p14_fig011396×1406px
P14 · p14_fig02999×651px
P14 · p14_fig01P14
P15 · p15_fig011082×1076px
P15 · p15_fig02979×750px
P27 · p27_fig01638×567px
P27 · p27_fig021186×1032px
P28 · p28_fig01752×1026px
P28 · p28_fig02757×808px
P28 · p28_fig01P28
Technical Specifications & Part Details (CH32M007E8U7)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH32M007E8U7 (QFN26C(3x3)) is a 26-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.90 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, PWM interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
25MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN26C(3x3))
Pin Count & Lead PitchN / e
26 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol26 auto-grouped pins
IPC-7351B Land Pattern26 pads · Pitch 0.40mm
IPC-7525 60% Solder PasteEPAD 2.10×2.75mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH32M007 (2)
QFN-32(4x4) · 33P
Mechanical Dimensions & Land Pattern (QFN26C(3x3))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.40 mm
Pins / Total PadsTopology
26P / 26Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN26C(3x3) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH32M007E8U7 (QFN26C(3x3))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH32M007E8U7 (QFN26C(3x3))?
Manufactured by WCH, the CH32M007E8U7 is housed in a QFN26C(3x3) package with 26 pins and a 0.40 mm lead pitch. Key pins include: 1 (PC4/A2: Multiplexed I/O & Peripheral Pin PC4/A2 (General)), 2 (PC5/RST/T2C1/CP0: Multiplexed I/O & Peripheral Pin PC5/RST/T2C1/CP0 (General)), 3 (VSS: Ground Reference Pin (VSS)), 4 (PD2/T2C3/CP2/A3: Multiplexed I/O & Peripheral Pin PD2/T2C3/CP2/A3 (General)), 5 (PD1/SWIO/T1C4/OP3: Multiplexed I/O & Peripheral Pin PD1/SWIO/T1C4/OP3 (General)), 6 (PD3/OP2/A4: Multiplexed I/O & Peripheral Pin PD3/OP2/A4 (General)).
What are the IPC-7351B PCB Footprint dimensions for CH32M007E8U7?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32M007E8U7 (QFN26C(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.40 mm, and 26 copper pads plus a central exposed thermal pad (EPAD) of 2.10 × 2.75 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32M007E8U7?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32M007E8U7 (WCH, QFN26C(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (26 pins) & CH32M007 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PC4/A2 | Digital_IO | Signal terminal PC4/A2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4/A2. Supported peripheral buses: General. |
| 2 | PC5/RST/T2C1/CP0 | Digital_IO | Signal terminal PC5/RST/T2C1/CP0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5/RST/T2C1/CP0. Supported peripheral buses: General. |
| 3 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 4 | PD2/T2C3/CP2/A3 | Digital_IO | Signal terminal PD2/T2C3/CP2/A3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD2/T2C3/CP2/A3. Supported peripheral buses: General. |
| 5 | PD1/SWIO/T1C4/OP3 | Digital_IO | Signal terminal PD1/SWIO/T1C4/OP3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD1/SWIO/T1C4/OP3. Supported peripheral buses: General. |
| 6 | PD3/OP2/A4 | Digital_IO | Signal terminal PD3/OP2/A4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD3/OP2/A4. Supported peripheral buses: General. |
| 7 | PD4/A7 | Digital_IO | Signal terminal PD4/A7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD4/A7. Supported peripheral buses: General. |
| 8 | PD5/CN1/A5 | Digital_IO | Signal terminal PD5/CN1/A5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD5/CN1/A5. Supported peripheral buses: General. |
| 9 | PD6/A6 | Digital_IO | Signal terminal PD6/A6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD6/A6. Supported peripheral buses: General. |
| 10 | PD7/OP1/A+ | Digital_IO | Signal terminal PD7/OP1/A+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD7/OP1/A+. Supported peripheral buses: General. |
| 11 | PA4/ON2/A- | Digital_IO | Signal terminal PA4/ON2/A- (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4/ON2/A-. Supported peripheral buses: General. |
| 12 | PA5/OO1/AO | Digital_IO | Signal terminal PA5/OO1/AO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5/OO1/AO. Supported peripheral buses: General. |
| 13 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 14 | VHREG | Digital_IO | Signal terminal VHREG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VHREG. Supported peripheral buses: General. |
| 15 | VHV | Digital_IO | Signal terminal VHV (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VHV. Supported peripheral buses: General. |
| 16 | HO1(PA3/T1C1) | Digital_IO | Signal terminal HO1(PA3/T1C1) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HO1(PA3/T1C1). Supported peripheral buses: General. |
| 17 | LO1(PA0/T1C1N) | Digital_IO | Signal terminal LO1(PA0/T1C1N) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LO1(PA0/T1C1N). Supported peripheral buses: General. |
| 18 | HO2(PB0/T1C2) | Digital_IO | Signal terminal HO2(PB0/T1C2) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HO2(PB0/T1C2). Supported peripheral buses: General. |
| 19 | LO2(PA2/T1C2N) | Digital_IO | Signal terminal LO2(PA2/T1C2N) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LO2(PA2/T1C2N). Supported peripheral buses: General. |
| 20 | HO3(PB1/T1C3) | Digital_IO | Signal terminal HO3(PB1/T1C3) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HO3(PB1/T1C3). Supported peripheral buses: General. |
| 21 | LO3(PD0/T1C3N) | Digital_IO | Signal terminal LO3(PD0/T1C3N) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LO3(PD0/T1C3N). Supported peripheral buses: General. |
| 22 | PB3/SWCK/T1BK/T2C2/CP1 | Digital_IO | Signal terminal PB3/SWCK/T1BK/T2C2/CP1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3/SWCK/T1BK/T2C2/CP1. Supported peripheral buses: General. |
| 23 | PC0/TX_/CPO | Digital_IO | Signal terminal PC0/TX_/CPO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0/TX_/CPO. Supported peripheral buses: General. |
| 24 | PC1 | Digital_IO | Signal terminal PC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C_SDA, SPI_NSS_. Supported peripheral buses: SPI, I2C. |
| 25 | PC2/CN0/SCL | Digital_IO | Signal terminal PC2/CN0/SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2/CN0/SCL. Supported peripheral buses: I2C. |
| 26 | PA1/ON0/A1 | Digital_IO | Signal terminal PA1/ON0/A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1/ON0/A1. Supported peripheral buses: General. |