MIC4604YMT-TR (TDFN-10-EP(2.5x2.5)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of MIC4604YMT-TR (TDFN-10-EP(2.5x2.5))?

Manufactured by MICROCHIP, the MIC4604YMT-TR is housed in a TDFN-10-EP(2.5x2.5) package with 11 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 5.5V to 16V. Key pins include: 1 (VDD: Power Supply Input (VDD — 5.5V to 16V)), 2 (HB: Multiplexed I/O & Peripheral Pin HB (General)), 3 (HO: Multiplexed I/O & Peripheral Pin HO (General)), 4 (HS: Multiplexed I/O & Peripheral Pin HS (General)), 5 (HI: Multiplexed I/O & Peripheral Pin HI (General)), 6 (LI: Multiplexed I/O & Peripheral Pin LI (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for MIC4604YMT-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MIC4604YMT-TR (TDFN-10-EP(2.5x2.5)) has a nominal body envelope of 2.50 × 2.50 mm, pitch e = 0.50 mm, and 11 copper pads plus a central exposed thermal pad (EPAD) of 1.90 × 1.20 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MIC4604YMT-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MIC4604YMT-TR (MICROCHIP, TDFN-10-EP(2.5x2.5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 2.50mm × 2.50mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (11/11)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	VDD	Power	Power Supply Input (VDD — 5.5V to 16V)
2	HB	I/O	Multiplexed I/O & Peripheral Pin HB (General)
3	HO	I/O	Multiplexed I/O & Peripheral Pin HO (General)
4	HS	I/O	Multiplexed I/O & Peripheral Pin HS (General)
5	HI	I/O	Multiplexed I/O & Peripheral Pin HI (General)
6	LI	I/O	Multiplexed I/O & Peripheral Pin LI (General)
7	VSS	GND	Ground Reference Pin (VSS)
8	LO	I/O	Multiplexed I/O & Peripheral Pin LO (General)
9	LO	I/O	Multiplexed I/O & Peripheral Pin LO (General)
10	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
11	EP	GND	Exposed Thermal & Ground Pad (EP)

PIN 1 VDD

Power

Power Supply Input (VDD — 5.5V to 16V)

Design note: Input supply for gate drivers . Decouple this pin to VSS with a >2 .2 µF capacitor Anodeconnectiontointernalbootstrapdiode . .

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

MIC4604YMT-TR (TDFN-10-EP(2.5x2.5)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

MIC4604YMT-TR (TDFN-10-EP(2.5x2.5)) - 2. Standard Pinout (Top View)

True package pinout (11 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

MIC4604YMT-TR (TDFN-10-EP(2.5x2.5)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

MIC4604YMT-TR (TDFN-10-EP(2.5x2.5)) - 4. Package Dimensions (D×E×A)

TDFN-10-EP(2.5x2.5) · 2.50×2.50mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

MIC4604YMT-TR (TDFN-10-EP(2.5x2.5)) - 5. Recommended Land Pattern

IPC-7351B Footprint (11 Pads)Expand ›

6. Application SchematicSCHEMATIC

MIC4604YMT-TR (TDFN-10-EP(2.5x2.5)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)

Showing 1–12 of 15 uncropped original figures for MIC4604

P1 · p01_fig01377×200px

85V Half-Bridge MOSFET Driver with up to 16V Programmable Gate Drive

P1 · p01_fig02761×704px

Package Types | MIC4604YMT 10-Pin TDFN (MT) (Top View) | EP | HS HI 5 | 1 VDD | NC | HB | HO | 10 NC | LO | VSS | LI | 9 | 8 | 7 | 2 | 3 | 4 | 6

P1 · p01_fig03636×559px

MIC4604YM | SOIC-8 (M) | (Top View) | 1 VDD | HB | HO | HS | 8 LO | VSS | LI | HI | 7 | 6 | 5 | 2 | 3 | 4

P2 · p02_fig011777×1055px

Functional Block Diagram

P2 · p02_fig021777×958px

Functional Block Diagram | HB | HS | HO | LO | HI | LI | DRIVER | DRIVER | UVLO | LEVEL | SHIFT | VDD | R Q | S Q | VSS | HB UVLO

P2 · p02_fig01P2

Datasheet Page 2 (p02_fig01)

P11 · p11_fig011777×1016px

FIGURE 4-1: Low-Side Driver Block Diagram. 4.4 High-Side Driver and Bootstrap Circuit

P11 · p11_fig02891×720px

FIGURE 4-2: High-Side Driver and Bootstrap Circuit Block Diagram.

P13 · p13_fig011777×876px

FIGURE 5-1: Negative HS Pin Voltage.

P21 · p21_fig021359×815px

MIC4604YMT-TR (TDFN-10-EP(2.5x2.5)) — ●, ▲, ▼Pin one index is identified by a dot, delta up, or delta down (triangle mark). | Underbar (_) and/or Overbar (⎯) symbol may not be to scale. | 3 e | 3 e

●, ▲, ▼Pin one index is identified by a dot, delta up, or delta down (triangle mark). | Underbar (_) and/or Overbar (⎯) symbol may not be to scale. | 3 e | 3 e

P21 · p21_fig02P21

Datasheet Page 21 (p21_fig02)

P22 · p22_fig011669×1766px

MIC4604YMT-TR (TDFN-10-EP(2.5x2.5)) — Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.

Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (MIC4604YMT-TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:MIC4604YMT-TR (TDFN-10-EP(2.5x2.5)) is a 10-pin standard electronic & interconnect component featuring a 2.50 × 2.50 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 5.5V to 16V supply operation across 40°C to +125°C with integrated Standard I/O / Passive interfaces.

Operating Supply VoltageV_CC / V_DD

5.5V to 16V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

40°C to +125°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

20 kHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

2.50 × 2.50 × 0.85 mm (A1=0.03 mm)

Package family: DFN (TDFN-10-EP(2.5x2.5))

Pin Count & Lead PitchN / e

10 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

Standard I/O / Passive

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol11 auto-grouped pins

IPC-7351B Land Pattern11 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteEPAD 1.90×1.20mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TDFN-10-EP(2.5x2.5))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

2.50 × 2.50 mm

Height (A) & Pitch (e)IPC-7351B

A=0.85mm · e=0.50mm

Pad Size (W × L)Level B

0.25 × 0.50 mm

Pins / Total PadsTopology

11P / 11Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit TDFN-10-EP(2.5x2.5)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MIC4604YMT-TR (TDFN-10-EP(2.5x2.5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MIC4604YMT-TR (TDFN-10-EP(2.5x2.5))?

Manufactured by MICROCHIP, the MIC4604YMT-TR is housed in a TDFN-10-EP(2.5x2.5) package with 11 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 5.5V to 16V. Key pins include: 1 (VDD: Power Supply Input (VDD — 5.5V to 16V)), 2 (HB: Multiplexed I/O & Peripheral Pin HB (General)), 3 (HO: Multiplexed I/O & Peripheral Pin HO (General)), 4 (HS: Multiplexed I/O & Peripheral Pin HS (General)), 5 (HI: Multiplexed I/O & Peripheral Pin HI (General)), 6 (LI: Multiplexed I/O & Peripheral Pin LI (General)).

What are the IPC-7351B PCB Footprint dimensions for MIC4604YMT-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MIC4604YMT-TR (TDFN-10-EP(2.5x2.5)) has a nominal body envelope of 2.50 × 2.50 mm, pitch e = 0.50 mm, and 11 copper pads plus a central exposed thermal pad (EPAD) of 1.90 × 1.20 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MIC4604YMT-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MIC4604YMT-TR (MICROCHIP, TDFN-10-EP(2.5x2.5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (11 pins) & MIC4604 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	VDD	Power_In	Primary positive power supply input (VDD) operating in the 5.5V to 16V domain (Max rating: 16.0V).
2	HB	Digital_IO	Signal terminal HB (I/O, 5.5V to 16V domain). Multiplexed alternate functions: HB. Supported peripheral buses: General.
3	HO	Digital_IO	Signal terminal HO (I/O, 5.5V to 16V domain). Multiplexed alternate functions: HO. Supported peripheral buses: General.
4	HS	Digital_IO	Signal terminal HS (I/O, 5.5V to 16V domain). Multiplexed alternate functions: HS. Supported peripheral buses: General.
5	HI	Digital_IO	Signal terminal HI (I/O, 5.5V to 16V domain). Multiplexed alternate functions: HI. Supported peripheral buses: General.
6	LI	Digital_IO	Signal terminal LI (I/O, 5.5V to 16V domain). Multiplexed alternate functions: LI. Supported peripheral buses: General.
7	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
8	LO	Digital_IO	Signal terminal LO (I/O, 5.5V to 16V domain). Multiplexed alternate functions: LO. Supported peripheral buses: General.
9	LO	Digital_IO	Signal terminal LO (I/O, 5.5V to 16V domain). Multiplexed alternate functions: LO. Supported peripheral buses: General.
10	NC	NC	Signal terminal NC (I/O, 5.5V to 16V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
11	EP	GND	Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.

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