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STM32F103RDY6TR (WLCSP-64(4.5x4.5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F103RDY6TR

STID: C2965365WLCSP-64(4.5x4.5) · 64 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F103RDY6TR (WLCSP-64(4.5x4.5))A1VDD_2A2PC10A3PD2A4PB3A5PB5A6BOOT0A7VSS_3A8VDD_3B1VSS_2B2PA14B3PC11B4PB4B5PB6B6PB9B7PC15 - OSC32B8PC14 - OSC32C1PA11C2PA12C3PA15C4PC12C5PB7C6VBATC7NRSTC8PC13TAMPER -D1PC9D2PA9D3PA10D4PA13D5PB8D6PC2D7PD1D8PD0H8PA2H7PA4H6PC4H5PC5H4PB0H3PB2H2VSS_1H1VDD_1G8VDDAG7PA3G6VDD_4G5PA6G4PA7G3PB10G2PB12G1PB13F8PC1F7VREF+F6PA0WKUP -F5VSS_4F4PB1F3PB11F2PB14F1PB15E8PC0E7VSSAE6PA1E5PA5E4PA8E3PC8E2PC7E1PC6Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1A2B2C2D2E2F2G2H2A3B3C3D3E3F3G3H3A4B4C4D4E4F4G4H4A5B5C5D5E5F5G5H5A6B6C6D6E6F6G6H6A7B7C7D7E7F7G7H7A8B8C8D8E8F8G8H8E=4.50mm · Pitch e=0.50mmD=4.50mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.50mm × 4.50mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VDD_2PowerPower Supply Input (VDD_2 — 3.3V VDD (Max 4.0V))
A2PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART)
A3PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
A4PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SPI, SWD/JTAG)
A5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C)
A6BOOT0IInput-Only Pin BOOT0 (General)
A7VSS_3GNDGround Reference Pin (VSS_3)
A8VDD_3PowerPower Supply Input (VDD_3 — 3.3V VDD (Max 4.0V))
B1VSS_2GNDGround Reference Pin (VSS_2)
B2PA14I/OMultiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
B3PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART)
B4PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI, SWD/JTAG)
B5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C)
B6PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
B7PC15 - OSC32 OUT(5)_I/OMultiplexed I/O & Peripheral Pin PC15 - OSC32 OUT(5)_ (RTC/CLK)
B8PC14 - OSC32 IN(5)_I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32 IN(5)_ (RTC/CLK)
C1PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, CAN)
C2PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART, CAN)
C3PA15I/OMultiplexed I/O & Peripheral Pin PA15 (SPI, SWD/JTAG)
C4PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART)
C5PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C)
C6VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
C7NRSTISystem Enable & Hardware Reset (NRST)
C8PC13TAMPER - - RTCI/OMultiplexed I/O & Peripheral Pin PC13TAMPER - - RTC (RTC/CLK)
D1PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
D2PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART)
D3PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART)
D4PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
D5PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
D6PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
D7PD1I/OMultiplexed I/O & Peripheral Pin PD1 (RTC/CLK)
D8PD0I/OMultiplexed I/O & Peripheral Pin PD0 (RTC/CLK)
E1PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
E2PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
E3PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
E4PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, RTC/CLK)
E5PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, DAC)
E6PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC)
E7VSSAGNDGround Reference Pin (VSSA)
E8PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
F1PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI)
F2PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
F3PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C)
F4PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
F5VSS_4GNDGround Reference Pin (VSS_4)
F6PA0WKUP -I/OMultiplexed I/O & Peripheral Pin PA0WKUP - (UART, ADC, PWM)
F7VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
F8PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
G1PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
G2PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)
G3PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, I2C)
G4PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC)
G5PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
G6VDD_4PowerPower Supply Input (VDD_4 — 3.3V VDD (Max 4.0V))
G7PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, PWM)
G8VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
H1VDD_1PowerPower Supply Input (VDD_1 — 3.3V VDD (Max 4.0V))
H2VSS_1GNDGround Reference Pin (VSS_1)
H3PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
H4PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
H5PC5I/OMultiplexed I/O & Peripheral Pin PC5 (ADC)
H6PC4I/OMultiplexed I/O & Peripheral Pin PC4 (ADC)
H7PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI, ADC, DAC)
H8PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
PIN A1 VDD_2
Power
Power Supply Input (VDD_2 — 3.3V VDD (Max 4.0V))
Design note: VDD_2
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F103RDY6TR (ST · WLCSP-64(4.5x4.5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F103RDY6TR (WLCSP-64(4.5x4.5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F103RDY6TR (WLCSP-64(4.5x4.5)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F103RDY6TR (WLCSP-64(4.5x4.5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F103RDY6TR (WLCSP-64(4.5x4.5)) - 4. Package Dimensions (D×E×A)
WLCSP-64(4.5x4.5) · 4.50×4.50mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F103RDY6TR (WLCSP-64(4.5x4.5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F103RDY6TR (WLCSP-64(4.5x4.5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for STM32F103
P30 · p30_fig01EXACT PACKAGE
STM32F103RDY6TR (WLCSP-64(4.5x4.5)) — Figure 8. STM32F103xC/D/E performance line
Figure 8. STM32F103xC/D/E performance line
P120 · p120_fig01EXACT PACKAGE
STM32F103RDY6TR (WLCSP-64(4.5x4.5)) — Figure 68. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale
Figure 68. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale
P121 · p121_fig01EXACT PACKAGE
STM32F103RDY6TR (WLCSP-64(4.5x4.5)) — Figure 69. WLCSP64 - 64-ball, 4.4757 x 4.4049 mm, 0.5 mm pitch wafer level chip scale
Figure 69. WLCSP64 - 64-ball, 4.4757 x 4.4049 mm, 0.5 mm pitch wafer level chip scale
P1 · p01_fig01881×446px
STM32F103RDY6TR (WLCSP-64(4.5x4.5)) — High-density performance line Arm®-based 32-bit MCU with 256 to 512KB
High-density performance line Arm®-based 32-bit MCU with 256 to 512KB
P30 · p30_fig01P30
STM32F103RDY6TR (WLCSP-64(4.5x4.5)) — Datasheet Page 30 (p30_fig01)
Datasheet Page 30 (p30_fig01)
P60 · p60_fig011546×483px
STM32F103RDY6TR (WLCSP-64(4.5x4.5)) — Figure 22. Typical application with an 8 MHz crystal
Figure 22. Typical application with an 8 MHz crystal
P60 · p60_fig01P60
STM32F103RDY6TR (WLCSP-64(4.5x4.5)) — Datasheet Page 60 (p60_fig01)
Datasheet Page 60 (p60_fig01)
P120 · p120_fig01P120
STM32F103RDY6TR (WLCSP-64(4.5x4.5)) — Datasheet Page 120 (p120_fig01)
Datasheet Page 120 (p120_fig01)
P121 · p121_fig01P121
STM32F103RDY6TR (WLCSP-64(4.5x4.5)) — Datasheet Page 121 (p121_fig01)
Datasheet Page 121 (p121_fig01)
P139 · p139_fig011546×2177px
STM32F103RDY6TR (WLCSP-64(4.5x4.5)) — STM32F103xC, STM32F103xD, STM32F103xE Revision history
STM32F103xC, STM32F103xD, STM32F103xE Revision history
P141 · p141_fig011546×2187px
STM32F103RDY6TR (WLCSP-64(4.5x4.5)) — STM32F103xC, STM32F103xD, STM32F103xE Revision history
STM32F103xC, STM32F103xD, STM32F103xE Revision history
P122 · p122_fig01All Packages in PDF
STM32F103RDY6TR (WLCSP-64(4.5x4.5)) — Figure 70. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline 6($7,1* 3/$1( &
Figure 70. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline 6($7,1* 3/$1( &

Technical Specifications & Part Details (STM32F103RDY6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F103RDY6TR (WLCSP-64(4.5x4.5)) is a 64-pin embedded microcontroller unit (mcu) featuring a 4.50 × 4.50 × 0.58 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
72 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.50 × 4.50 × 0.58 mm (A1=0.23 mm)
Package family: WLCSP (WLCSP-64(4.5x4.5))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0, PB2): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-64(4.5x4.5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.50 × 4.50 mm
Height (A) & Pitch (e)IPC-7351B
A=0.58mm · e=0.50mm
Pad Size (W × L)Level B
0.26 × 0.26 mm
Pins / Total PadsTopology
64P / 64Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1, C2, C3
BOM
3× 100nF (0.1µF) 50V X7R
0402 / 0603
Digital supply decoupling caps for VDD_1..3 (Pins 24, 36, 48) — place < 1.5mm from each VDD pin.
C4
BOM
4.7µF ~ 10µF 10V X5R
0603 / 0805
Bulk decoupling capacitor for main VDD rail — place near 3.3V power entry to the MCU.
C5, C6 + FB1
BOM
100nF + 1µF + Ferrite 600Ω@100MHz
0402 / 0603
Analog rail filter for VDDA/VSSA (Pins 8, 9) 12-bit ADC — isolate digital switching noise.
Y1 + C7, C8
BOM
8MHz Crystal (CL=12pF) + 2× 18pF NP0
SMD-3225 + 0402
Main HSE oscillator crystal (Pin 5 PD0, Pin 6 PD1) — route matched traces < 4mm with GND guard ring.
STM32F103CBT6
STMicroelectronics
100% Drop-in100% Drop-in (128KB Flash Upgrade) — identical LQFP-48 pinout with doubled Flash capacity.
GD32F103C8T6
GigaDevice
Pin-to-Pin LQFP-48 (108MHz)Pin-to-Pin LQFP-48 (108MHz) — higher core clock; verify Flash wait-states & USB timing.
APM32F103C8T6
Geehy
Pin-to-Pin LQFP-48 (96MHz)Pin-to-Pin LQFP-48 (96MHz) — direct hardware replacement, register-compatible with STM32F1.

Technical Frequently Asked Questions (FAQ) — STM32F103RDY6TR (WLCSP-64(4.5x4.5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F103RDY6TR (WLCSP-64(4.5x4.5))?

Manufactured by ST, the STM32F103RDY6TR is housed in a WLCSP-64(4.5x4.5) package with 64 pins and a 0.50 mm lead pitch. Key pins include: A1 (VDD_2: Power Supply Input (VDD_2 — 3.3V VDD (Max 4.0V))), A2 (PC10: Multiplexed I/O & Peripheral Pin PC10 (UART)), A3 (PD2: Multiplexed I/O & Peripheral Pin PD2 (UART)), A4 (PB3: Multiplexed I/O & Peripheral Pin PB3 (SPI, SWD/JTAG)), A5 (PB5: Multiplexed I/O & Peripheral Pin PB5 (SPI, I2C)), A6 (BOOT0: Input-Only Pin BOOT0 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32F103RDY6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F103RDY6TR (WLCSP-64(4.5x4.5)) has a nominal body envelope of 4.50 × 4.50 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F103RDY6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F103RDY6TR (ST, WLCSP-64(4.5x4.5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & STM32F103 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VDD_2Power_InPrimary positive power supply input (VDD_2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A2PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: UART.
A3PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
A4PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: SPI, SWD/JTAG.
A5PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SMBA, SPI3_MOSI_. Supported peripheral buses: SPI, I2C.
A6BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
A7VSS_3GND0V electrical ground return terminal (VSS_3) for internal core logic, I/O drivers, and analog sub-blocks.
A8VDD_3Power_InPrimary positive power supply input (VDD_3) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B1VSS_2GND0V electrical ground return terminal (VSS_2) for internal core logic, I/O drivers, and analog sub-blocks.
B2PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: SWD/JTAG.
B3PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: UART.
B4PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: SPI, SWD/JTAG.
B5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
B6PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
B7PC15 - OSC32 OUT(5)_Digital_IOSignal terminal PC15 - OSC32 OUT(5)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15 - OSC32 OUT(5)_. Supported peripheral buses: RTC/CLK.
B8PC14 - OSC32 IN(5)_Digital_IOSignal terminal PC14 - OSC32 IN(5)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14 - OSC32 IN(5)_. Supported peripheral buses: RTC/CLK.
C1PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: USB, UART, CAN.
C2PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: USB, UART, CAN.
C3PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_NSS. Supported peripheral buses: SPI, SWD/JTAG.
C4PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: UART.
C5PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: I2C.
C6VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
C8PC13TAMPER - - RTCDigital_IOSignal terminal PC13TAMPER - - RTC (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13TAMPER - - RTC. Supported peripheral buses: RTC/CLK.
D1PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
D2PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART.
D3PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART.
D4PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
D5PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
D6PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: ADC.
D7PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: RTC/CLK.
D8PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: RTC/CLK.
E1PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
E2PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
E3PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
E4PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, RTC/CLK.
E5PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, DAC.
E6PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC.
E7VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
E8PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
F1PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI.
F2PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI, PWM.
F3PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: UART, I2C.
F4PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM.
F5VSS_4GND0V electrical ground return terminal (VSS_4) for internal core logic, I/O drivers, and analog sub-blocks.
F6PA0WKUP -Digital_IOSignal terminal PA0WKUP - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0WKUP -. Supported peripheral buses: UART, ADC, PWM.
F7VREF+AnalogSignal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
F8PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: ADC.
G1PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, PWM.
G2PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_NSS, I2C2_SMBA. Supported peripheral buses: UART, SPI, I2C.
G3PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C2_SCL. Supported peripheral buses: UART, I2C.
G4PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC.
G5PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC.
G6VDD_4Power_InPrimary positive power supply input (VDD_4) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
G7PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, PWM.
G8VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
H1VDD_1Power_InPrimary positive power supply input (VDD_1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
H2VSS_1GND0V electrical ground return terminal (VSS_1) for internal core logic, I/O drivers, and analog sub-blocks.
H3PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
H4PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
H5PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: ADC.
H6PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC.
H7PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: SPI, ADC, DAC.
H8PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
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