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CH554T (TSSOP-20) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH554T

WCHID: C2928938TSSOP-20 · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH554T (TSSOP-20)1IO12IO233V34P1.6/MISO/RX5P1.7/SCK/TXD6RST/T2EX_/CA7P1.0/T2/CAP18IO09P3.1/PWM2_/T10P3.0/PWM1_/R20V3319VCC/VDD18GND/VSS17P1.2/XI/RXD_16P1.3/XO/TXD_15P3.7/UDM14P3.6/UDP13P3.5/T112P3.4/PWM2/RX11P3.3/INT1Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.217.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=4.40mm · Pitch e=0.65mmD=6.50mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 4.40mm × 6.50mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1IO1I/OGeneral Purpose Digital I/O Pin IO1
2IO2I/OGeneral Purpose Digital I/O Pin IO2
33V3Power3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4P1.6/MISO/RXD1/TIN4I/OMultiplexed I/O & Peripheral Pin P1.6/MISO/RXD1/TIN4 (UART, SPI)
5P1.7/SCK/TXD1/TIN5I/OMultiplexed I/O & Peripheral Pin P1.7/SCK/TXD1/TIN5 (UART, SPI)
6RST/T2EX_/CAP2_I/OMultiplexed I/O & Peripheral Pin RST/T2EX_/CAP2_ (General)
7P1.0/T2/CAP1/TIN0I/OMultiplexed I/O & Peripheral Pin P1.0/T2/CAP1/TIN0 (General)
8IO0I/OGPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9P3.1/PWM2_/TXDI/OMultiplexed I/O & Peripheral Pin P3.1/PWM2_/TXD (UART, PWM)
10P3.0/PWM1_/RXDI/OMultiplexed I/O & Peripheral Pin P3.0/PWM1_/RXD (UART, PWM)
11P3.3/INT1I/OMultiplexed I/O & Peripheral Pin P3.3/INT1 (General)
12P3.4/PWM2/RXD1_/T0I/OMultiplexed I/O & Peripheral Pin P3.4/PWM2/RXD1_/T0 (UART, PWM)
13P3.5/T1I/OMultiplexed I/O & Peripheral Pin P3.5/T1 (General)
14P3.6/UDPI/OMultiplexed I/O & Peripheral Pin P3.6/UDP (General)
15P3.7/UDMI/OMultiplexed I/O & Peripheral Pin P3.7/UDM (General)
16P1.3/XO/TXD_I/OMultiplexed I/O & Peripheral Pin P1.3/XO/TXD_ (UART, RTC/CLK)
17P1.2/XI/RXD_I/OMultiplexed I/O & Peripheral Pin P1.2/XI/RXD_ (UART, RTC/CLK)
18GND/VSSGNDGround Reference Pin (GND/VSS)
19VCC/VDDPowerPower Supply Input (VCC/VDD — 3.3V / 5.0V Standard Logic)
20V33PowerPower Supply Input (V33 — 3.3V / 5.0V Standard Logic)
PIN 1 IO1
I/O
General Purpose Digital I/O Pin IO1
Design note: 3.3V logic domain (3.6V absolute max), 40mA max drive current.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH554T (WCH · TSSOP-20)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH554T (TSSOP-20) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH554T (TSSOP-20) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH554T (TSSOP-20) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH554T (TSSOP-20) - 4. Package Dimensions (D×E×A)
TSSOP-20 · 4.40×6.50mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH554T (TSSOP-20) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH554T (TSSOP-20) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for CH554
P1 · p01_fig011684×868px
CH554T (TSSOP-20) — CH554 内置了ADC 模数转换、触摸按键电容检测、3 组定时器和信号捕捉及PWM、双异步串口、 SPI 等功能模块，支持USB-Host 主机模式和USB-Device 设备模式。
CH554 内置了ADC 模数转换、触摸按键电容检测、3 组定时器和信号捕捉及PWM、双异步串口、 SPI 等功能模块，支持USB-Host 主机模式和USB-Device 设备模式。
P2 · p02_fig011865×1645px
CH554T (TSSOP-20) — 耗睡眠，支持USB、UART0、UART1、SPI0 以及部分GPIO 外部唤醒。 l 芯片内置唯一ID 号。
耗睡眠，支持USB、UART0、UART1、SPI0 以及部分GPIO 外部唤醒。 l 芯片内置唯一ID 号。
P2 · p02_fig01P2
CH554T (TSSOP-20) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P18 · p18_fig011757×2025px
CH554T (TSSOP-20) — CH554 手册 18 | CLOCK_CFG B9h 系统时钟配置寄存器 83h | 系统时钟配置寄存器(CLOCK_CFG)，仅在安全模式下可写： | 位 名称 访问 描述 复位值 | 7 bOSC_EN_INT RW | 内部时钟振荡器使能，该位为1 使能内部时钟振荡器 并且选用内部时钟；该位为0 关闭内部时钟振荡器并 且选用外部晶体振荡器提供时钟 | 1 | 6 bOSC_EN_XT RW | 外部晶体振荡器使能，该位为1 则P1.2/P1.3 引脚作 为XI/XO
CH554 手册 18 | CLOCK_CFG B9h 系统时钟配置寄存器 83h | 系统时钟配置寄存器(CLOCK_CFG)，仅在安全模式下可写： | 位 名称 访问 描述 复位值 | 7 bOSC_EN_INT RW | 内部时钟振荡器使能，该位为1 使能内部时钟振荡器 并且选用内部时钟；该位为0 关闭内部时钟振荡器并 且选用外部晶体振荡器提供时钟 | 1 | 6 bOSC_EN_XT RW | 外部晶体振荡器使能，该位为1 则P1.2/P1.3 引脚作 为XI/XO
P18 · p18_fig01P18
CH554T (TSSOP-20) — Datasheet Page 18 (p18_fig01)
Datasheet Page 18 (p18_fig01)
P22 · p22_fig011757×433px
CH554T (TSSOP-20) — 位 名称 访问 描述 复位值
位 名称 访问 描述 复位值
P23 · p23_fig011664×915px
CH554T (TSSOP-20) — 图10.2.1 I/O 引脚等效原理图
图10.2.1 I/O 引脚等效原理图
P37 · p37_fig011757×2277px
CH554T (TSSOP-20) — 模式0：bSn_MST_CLK = 0
模式0：bSn_MST_CLK = 0
P37 · p37_fig021496×347px
CH554T (TSSOP-20) — 模式0：bSn_MST_CLK = 0
模式0：bSn_MST_CLK = 0
P53 · p53_fig011757×2440px
CH554T (TSSOP-20) — 18、参数
18、参数
P54 · p54_fig011757×2224px
CH554T (TSSOP-20) — CH554 手册 54 | ISLP3L bLDO3V3_OFF=1 关闭LDO， | 完全睡眠后的总电源电流 0.004 0.015 mA | IADC3 ADC 模数转换模块工作电流 150 500 uA | ICMP3 电压比较器模块工作电流 70 300 uA | ITKEY3 触摸按键电容检测模块工作电流 130 200 uA | VIL3 低电平输入电压 -0.4 0.8 V | VIH3 高电平输入电压 1.9 VCC+0.4 V | VOL3 低电平输出电压(
CH554 手册 54 | ISLP3L bLDO3V3_OFF=1 关闭LDO， | 完全睡眠后的总电源电流 0.004 0.015 mA | IADC3 ADC 模数转换模块工作电流 150 500 uA | ICMP3 电压比较器模块工作电流 70 300 uA | ITKEY3 触摸按键电容检测模块工作电流 130 200 uA | VIL3 低电平输入电压 -0.4 0.8 V | VIH3 高电平输入电压 1.9 VCC+0.4 V | VOL3 低电平输出电压(
P54 · p54_fig01P54
CH554T (TSSOP-20) — Datasheet Page 54 (p54_fig01)
Datasheet Page 54 (p54_fig01)

Technical Specifications & Part Details (CH554T)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH554T (TSSOP-20) is a 20-pin standard electronic & interconnect component featuring a 6.50 × 4.40 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
6MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.50 × 4.40 × 1.00 mm (A1=0.10 mm)
Package family: TSSOP (TSSOP-20)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TSSOP-20)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.50 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.45 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TSSOP-20
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH554T (TSSOP-20)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH554T (TSSOP-20)?

Manufactured by WCH, the CH554T is housed in a TSSOP-20 package with 20 pins and a 0.65 mm lead pitch. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (P1.6/MISO/RXD1/TIN4: Multiplexed I/O & Peripheral Pin P1.6/MISO/RXD1/TIN4 (UART, SPI)), 5 (P1.7/SCK/TXD1/TIN5: Multiplexed I/O & Peripheral Pin P1.7/SCK/TXD1/TIN5 (UART, SPI)), 6 (RST/T2EX_/CAP2_: Multiplexed I/O & Peripheral Pin RST/T2EX_/CAP2_ (General)).

What are the IPC-7351B PCB Footprint dimensions for CH554T?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH554T (TSSOP-20) has a nominal body envelope of 4.40 × 6.50 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH554T?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH554T (WCH, TSSOP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & CH554 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1IO1Digital_IOGeneral Purpose Digital I/O Pin IO1
2IO2Digital_IOGeneral Purpose Digital I/O Pin IO2
33V3Power_In3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4P1.6/MISO/RXD1/TIN4Digital_IOSignal terminal P1.6/MISO/RXD1/TIN4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.6/MISO/RXD1/TIN4. Supported peripheral buses: UART, SPI.
5P1.7/SCK/TXD1/TIN5Digital_IOSignal terminal P1.7/SCK/TXD1/TIN5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.7/SCK/TXD1/TIN5. Supported peripheral buses: UART, SPI.
6RST/T2EX_/CAP2_Digital_IOSignal terminal RST/T2EX_/CAP2_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST/T2EX_/CAP2_. Supported peripheral buses: General.
7P1.0/T2/CAP1/TIN0Digital_IOSignal terminal P1.0/T2/CAP1/TIN0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.0/T2/CAP1/TIN0. Supported peripheral buses: General.
8IO0Digital_IOGPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9P3.1/PWM2_/TXDDigital_IOSignal terminal P3.1/PWM2_/TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.1/PWM2_/TXD. Supported peripheral buses: UART, PWM.
10P3.0/PWM1_/RXDDigital_IOSignal terminal P3.0/PWM1_/RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.0/PWM1_/RXD. Supported peripheral buses: UART, PWM.
11P3.3/INT1Digital_IOSignal terminal P3.3/INT1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.3/INT1. Supported peripheral buses: General.
12P3.4/PWM2/RXD1_/T0Digital_IOSignal terminal P3.4/PWM2/RXD1_/T0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.4/PWM2/RXD1_/T0. Supported peripheral buses: UART, PWM.
13P3.5/T1Digital_IOSignal terminal P3.5/T1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.5/T1. Supported peripheral buses: General.
14P3.6/UDPDigital_IOSignal terminal P3.6/UDP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.6/UDP. Supported peripheral buses: General.
15P3.7/UDMDigital_IOSignal terminal P3.7/UDM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.7/UDM. Supported peripheral buses: General.
16P1.3/XO/TXD_Digital_IOSignal terminal P1.3/XO/TXD_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.3/XO/TXD_. Supported peripheral buses: UART, RTC/CLK.
17P1.2/XI/RXD_Digital_IOSignal terminal P1.2/XI/RXD_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.2/XI/RXD_. Supported peripheral buses: UART, RTC/CLK.
18GND/VSSGND0V electrical ground return terminal (GND/VSS) for internal core logic, I/O drivers, and analog sub-blocks.
19VCC/VDDPower_InPrimary positive power supply input (VCC/VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
20V33Power_InPrimary positive power supply input (V33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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