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MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

MIC45116-2YMP-TR

MICROCHIPID: C219488QFN-52-EP(8x8.5) · 51 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · MIC45116-2YMP-TR (QFN-52-EP(8x8.5))1PVIN2PVIN4PV DD5BST6BST8SW9SW10SW12PV IN13VOUT14VOUT15VOUT16VOUT17VOUT18VOUT19VOUT20VOUT21VOUT23NC24NC25NC26PGND27NC28NC29NC30NC56PGNDePAD55VOUTePAD54PGNDePAD53SWePAD52PV IN51SW50SW49SW48SW47I LIM45P GND44PV DD435V DD42P GND41NC40NC39V IN38EN37PG36FB35PGND34NC33NC32NC31PGNDGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.838.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
1245689101213141516171819202123242526272829303132333435363738394041424344454748495051521111155588888111212121212121216161616161616161616162323233232323232323232434444474848484848484853555535353535353545556E=8.00mm · Pitch e=0.50mmD=8.50mm-6-5-4-3-2-1012345676543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.50mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (51/51)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PVINPowerPower Supply Input (PVIN — 4.75V to 20V)
2PVINPowerPower Supply Input (PVIN — 4.75V to 20V)
4PV DDI/OMultiplexed I/O & Peripheral Pin PV DD (General)
5BSTI/OMultiplexed I/O & Peripheral Pin BST (General)
6BSTI/OMultiplexed I/O & Peripheral Pin BST (General)
8SWI/OMultiplexed I/O & Peripheral Pin SW (General)
9SWI/OMultiplexed I/O & Peripheral Pin SW (General)
10SWI/OMultiplexed I/O & Peripheral Pin SW (General)
12PV INI/OMultiplexed I/O & Peripheral Pin PV IN (General)
13VOUTPowerRegulated Power Output (VOUT — 4.75V to 20V)
14VOUTPowerRegulated Power Output (VOUT — 4.75V to 20V)
15VOUTPowerRegulated Power Output (VOUT — 4.75V to 20V)
16VOUTPowerRegulated Power Output (VOUT — 4.75V to 20V)
17VOUTPowerRegulated Power Output (VOUT — 4.75V to 20V)
18VOUTPowerRegulated Power Output (VOUT — 4.75V to 20V)
19VOUTPowerRegulated Power Output (VOUT — 4.75V to 20V)
20VOUTPowerRegulated Power Output (VOUT — 4.75V to 20V)
21VOUTPowerRegulated Power Output (VOUT — 4.75V to 20V)
23NCI/OMultiplexed I/O & Peripheral Pin NC (General)
24NCI/OMultiplexed I/O & Peripheral Pin NC (General)
25NCI/OMultiplexed I/O & Peripheral Pin NC (General)
26PGNDGNDGround Reference Pin (PGND)
27NCI/OMultiplexed I/O & Peripheral Pin NC (General)
28NCI/OMultiplexed I/O & Peripheral Pin NC (General)
29NCI/OMultiplexed I/O & Peripheral Pin NC (General)
30NCI/OMultiplexed I/O & Peripheral Pin NC (General)
31PGNDGNDGround Reference Pin (PGND)
32NCI/OMultiplexed I/O & Peripheral Pin NC (General)
33NCI/OMultiplexed I/O & Peripheral Pin NC (General)
34NCI/OMultiplexed I/O & Peripheral Pin NC (General)
35PGNDGNDGround Reference Pin (PGND)
36FBI/OMultiplexed I/O & Peripheral Pin FB (General)
37PGI/OMultiplexed I/O & Peripheral Pin PG (General)
38ENISystem Enable & Hardware Reset (EN)
39V INI/OMultiplexed I/O & Peripheral Pin V IN (General)
40NCI/OMultiplexed I/O & Peripheral Pin NC (General)
41NCI/OMultiplexed I/O & Peripheral Pin NC (General)
42P GNDGNDGround Reference Pin (P GND)
435V DDPowerRegulated Power Output (5V DD — 4.75V to 20V)
44PV DDI/OMultiplexed I/O & Peripheral Pin PV DD (General)
45P GNDGNDGround Reference Pin (P GND)
47I LIMI/OMultiplexed I/O & Peripheral Pin I LIM (General)
48SWI/OMultiplexed I/O & Peripheral Pin SW (General)
49SWI/OMultiplexed I/O & Peripheral Pin SW (General)
50SWI/OMultiplexed I/O & Peripheral Pin SW (General)
51SWI/OMultiplexed I/O & Peripheral Pin SW (General)
52PV INI/OMultiplexed I/O & Peripheral Pin PV IN (General)
53SWePADGNDGround Reference Pin (SWePAD)
54PGNDePADGNDGround Reference Pin (PGNDePAD)
55VOUTePADGNDGround Reference Pin (VOUTePAD)
56PGNDePADGNDGround Reference Pin (PGNDePAD)
PIN 1 PVIN
Power
Power Supply Input (PVIN — 4.75V to 20V)
Design note: Primary positive power supply input (PVIN) operating in the 4.75V to 20V domain (Max rating: 20.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: MIC45116-2YMP-TR (MICROCHIP · QFN-52-EP(8x8.5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) - 2. Standard Pinout (Top View)
True package pinout (51 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) - 4. Package Dimensions (D×E×A)
QFN-52-EP(8x8.5) · 8.00×8.50mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (115 Pads)Expand ›
6. Application SchematicSCHEMATIC
MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for MIC45116
P1 · p01_fig01377×200px
MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) — 20V/6A DC/DC Power Module
20V/6A DC/DC Power Module
P1 · p01_fig021777×946px
MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) — Typical Application Circuit
Typical Application Circuit
P1 · p01_fig02P1
MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P2 · p02_fig011587×1794px
MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) — MIC45116 | Package Type | MIC45116 8x8x3 QFN (MP) | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 17 18 19 20 21 22 23 24 25 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 43 44 45
MIC45116 | Package Type | MIC45116 8x8x3 QFN (MP) | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 17 18 19 20 21 22 23 24 25 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 43 44 45
P2 · p02_fig01P2
MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P21 · p21_fig011777×1309px
MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) — FIGURE 4-4: MIC45116-1 Control Loop (Discontinuous Mode).
FIGURE 4-4: MIC45116-1 Control Loop (Discontinuous Mode).
P23 · p23_fig011777×1790px
MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) — 5.0 APPLICATION INFORMATION
5.0 APPLICATION INFORMATION
P24 · p24_fig011778×1179px
MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) — FIGURE 5-1: Voltage Divider Configuration. The output voltage is determined by Equation 5-8: EQUATION 5-8:
FIGURE 5-1: Voltage Divider Configuration. The output voltage is determined by Equation 5-8: EQUATION 5-8:
P24 · p24_fig021777×1539px
MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) — FIGURE 5-1: Voltage Divider Configuration. The output voltage is determined by Equation 5-8: EQUATION 5-8:
FIGURE 5-1: Voltage Divider Configuration. The output voltage is determined by Equation 5-8: EQUATION 5-8:
P27 · p27_fig01767×992px
MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) — FIGURE 6-1: Top and Bottom of a Four-Layer Board.
FIGURE 6-1: Top and Bottom of a Four-Layer Board.
P28 · p28_fig011612×777px
MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) — FIGURE 7-1: Package Bottom View vs. PCB Recommended Exposed Metal Trace. Please note the exposed metal trace is a “mirror image” of the package bottom view.
FIGURE 7-1: Package Bottom View vs. PCB Recommended Exposed Metal Trace. Please note the exposed metal trace is a “mirror image” of the package bottom view.
P30 · p30_fig011570×1875px
MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) — MIC45116 | 8.0 PACKAGING INFORMATION | 8.1 Package Marking Information | 52-Pin QFN* Example | XXX XXXXX-X WNNN | MIC 45116-1 6420 | ●, ▲, ▼Pin one index is identified by a dot, delta up, or delta down (triangle mark). | Underbar (_) symbol
MIC45116 | 8.0 PACKAGING INFORMATION | 8.1 Package Marking Information | 52-Pin QFN* Example | XXX XXXXX-X WNNN | MIC 45116-1 6420 | ●, ▲, ▼Pin one index is identified by a dot, delta up, or delta down (triangle mark). | Underbar (_) symbol
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (MIC45116-2YMP-TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) is a 50-pin standard electronic & interconnect component featuring a 8.50 × 8.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 4.75V to 20V supply operation across 40°C to +125°C with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
4.75V to 20V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
40°C to +125°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
600 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
8.50 × 8.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-52-EP(8x8.5))
Pin Count & Lead PitchN / e
50 Pins | Pitch e = 0.50 mm (19.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol51 auto-grouped pins
OK
IPC-7351B Land Pattern115 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 7.80×7.80mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-52-EP(8x8.5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.50 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.50mm
Pad Size (W × L)Level B
0.25 × 0.80 mm
Pins / Total PadsTopology
51P / 115Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-52-EP(8x8.5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MIC45116-2YMP-TR (QFN-52-EP(8x8.5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MIC45116-2YMP-TR (QFN-52-EP(8x8.5))?

Manufactured by MICROCHIP, the MIC45116-2YMP-TR is housed in a QFN-52-EP(8x8.5) package with 51 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 4.75V to 20V. Key pins include: 1 (PVIN: Power Supply Input (PVIN — 4.75V to 20V)), 2 (PVIN: Power Supply Input (PVIN — 4.75V to 20V)), 4 (PV DD: Multiplexed I/O & Peripheral Pin PV DD (General)), 5 (BST: Multiplexed I/O & Peripheral Pin BST (General)), 6 (BST: Multiplexed I/O & Peripheral Pin BST (General)), 8 (SW: Multiplexed I/O & Peripheral Pin SW (General)).

What are the IPC-7351B PCB Footprint dimensions for MIC45116-2YMP-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MIC45116-2YMP-TR (QFN-52-EP(8x8.5)) has a nominal body envelope of 8.00 × 8.50 mm, pitch e = 0.50 mm, and 115 copper pads plus a central exposed thermal pad (EPAD) of 7.80 × 7.80 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MIC45116-2YMP-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MIC45116-2YMP-TR (MICROCHIP, QFN-52-EP(8x8.5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (51 pins) & MIC45116 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PVINPower_InPrimary positive power supply input (PVIN) operating in the 4.75V to 20V domain (Max rating: 20.0V).
2PVINPower_InPrimary positive power supply input (PVIN) operating in the 4.75V to 20V domain (Max rating: 20.0V).
4PV DDDigital_IOSignal terminal PV DD (I/O, 4.75V to 20V domain). Multiplexed alternate functions: PV DD. Supported peripheral buses: General.
5BSTDigital_IOSignal terminal BST (I/O, 4.75V to 20V domain). Multiplexed alternate functions: BST. Supported peripheral buses: General.
6BSTDigital_IOSignal terminal BST (I/O, 4.75V to 20V domain). Multiplexed alternate functions: BST. Supported peripheral buses: General.
8SWDigital_IOSignal terminal SW (I/O, 4.75V to 20V domain). Multiplexed alternate functions: SW. Supported peripheral buses: General.
9SWDigital_IOSignal terminal SW (I/O, 4.75V to 20V domain). Multiplexed alternate functions: SW. Supported peripheral buses: General.
10SWDigital_IOSignal terminal SW (I/O, 4.75V to 20V domain). Multiplexed alternate functions: SW. Supported peripheral buses: General.
12PV INDigital_IOSignal terminal PV IN (I/O, 4.75V to 20V domain). Multiplexed alternate functions: PV IN. Supported peripheral buses: General.
13VOUTPower_OutRegulated power output rail (VOUT) operating in the 4.75V to 20V domain (Max rating: 20.0V).
14VOUTPower_OutRegulated power output rail (VOUT) operating in the 4.75V to 20V domain (Max rating: 20.0V).
15VOUTPower_OutRegulated power output rail (VOUT) operating in the 4.75V to 20V domain (Max rating: 20.0V).
16VOUTPower_OutRegulated power output rail (VOUT) operating in the 4.75V to 20V domain (Max rating: 20.0V).
17VOUTPower_OutRegulated power output rail (VOUT) operating in the 4.75V to 20V domain (Max rating: 20.0V).
18VOUTPower_OutRegulated power output rail (VOUT) operating in the 4.75V to 20V domain (Max rating: 20.0V).
19VOUTPower_OutRegulated power output rail (VOUT) operating in the 4.75V to 20V domain (Max rating: 20.0V).
20VOUTPower_OutRegulated power output rail (VOUT) operating in the 4.75V to 20V domain (Max rating: 20.0V).
21VOUTPower_OutRegulated power output rail (VOUT) operating in the 4.75V to 20V domain (Max rating: 20.0V).
23NCNCSignal terminal NC (I/O, 4.75V to 20V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
24NCNCSignal terminal NC (I/O, 4.75V to 20V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
25NCNCSignal terminal NC (I/O, 4.75V to 20V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
26PGNDGND0V electrical ground return terminal (PGND) for internal core logic, I/O drivers, and analog sub-blocks.
27NCNCSignal terminal NC (I/O, 4.75V to 20V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
28NCNCSignal terminal NC (I/O, 4.75V to 20V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
29NCNCSignal terminal NC (I/O, 4.75V to 20V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
30NCNCSignal terminal NC (I/O, 4.75V to 20V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
31PGNDGND0V electrical ground return terminal (PGND) for internal core logic, I/O drivers, and analog sub-blocks.
32NCNCSignal terminal NC (I/O, 4.75V to 20V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
33NCNCSignal terminal NC (I/O, 4.75V to 20V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
34NCNCSignal terminal NC (I/O, 4.75V to 20V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
35PGNDGND0V electrical ground return terminal (PGND) for internal core logic, I/O drivers, and analog sub-blocks.
36FBDigital_IOSignal terminal FB (I/O, 4.75V to 20V domain). Multiplexed alternate functions: FB. Supported peripheral buses: General.
37PGOpen_DrainSignal terminal PG (I/O, 4.75V to 20V domain). Multiplexed alternate functions: PG. Supported peripheral buses: General.
38ENDigital_IOChip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset.
39V INDigital_IOSignal terminal V IN (I/O, 4.75V to 20V domain). Multiplexed alternate functions: V IN. Supported peripheral buses: General.
40NCNCSignal terminal NC (I/O, 4.75V to 20V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
41NCNCSignal terminal NC (I/O, 4.75V to 20V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
42P GNDGND0V electrical ground return terminal (P GND) for internal core logic, I/O drivers, and analog sub-blocks.
435V DDPower_OutRegulated power output rail (5V DD) operating in the 4.75V to 20V domain (Max rating: 20.0V).
44PV DDDigital_IOSignal terminal PV DD (I/O, 4.75V to 20V domain). Multiplexed alternate functions: PV DD. Supported peripheral buses: General.
45P GNDGND0V electrical ground return terminal (P GND) for internal core logic, I/O drivers, and analog sub-blocks.
47I LIMDigital_IOSignal terminal I LIM (I/O, 4.75V to 20V domain). Multiplexed alternate functions: I LIM. Supported peripheral buses: General.
48SWDigital_IOSignal terminal SW (I/O, 4.75V to 20V domain). Multiplexed alternate functions: SW. Supported peripheral buses: General.
49SWDigital_IOSignal terminal SW (I/O, 4.75V to 20V domain). Multiplexed alternate functions: SW. Supported peripheral buses: General.
50SWDigital_IOSignal terminal SW (I/O, 4.75V to 20V domain). Multiplexed alternate functions: SW. Supported peripheral buses: General.
51SWDigital_IOSignal terminal SW (I/O, 4.75V to 20V domain). Multiplexed alternate functions: SW. Supported peripheral buses: General.
52PV INDigital_IOSignal terminal PV IN (I/O, 4.75V to 20V domain). Multiplexed alternate functions: PV IN. Supported peripheral buses: General.
53SWePADGND0V electrical ground return terminal (SWePAD) for internal core logic, I/O drivers, and analog sub-blocks.
54PGNDePADGND0V electrical ground return terminal (PGNDePAD) for internal core logic, I/O drivers, and analog sub-blocks.
55VOUTePADGND0V electrical ground return terminal (VOUTePAD) for internal core logic, I/O drivers, and analog sub-blocks.
56PGNDePADGND0V electrical ground return terminal (PGNDePAD) for internal core logic, I/O drivers, and analog sub-blocks.
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