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PIC24F32KA302-I/ML (QFN-28-EP(6x6)) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC24F32KA302-I/ML

MICROCHIPID: C219287QFN-28-EP(6x6) · 29 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC24F32KA302-I/ML (QFN-28-EP(6x6))1RA52VREF+3VREF-4ULPWU5U2RX6U1RX7RA28RA39U2RTS10U2CTS11U1TX12U1CTS13U1RTS14RA615SS229EP28IO3327IO4726#MCLR/VPP/RA25Vdd/AVdd24Vss/AVss23IO1222IO1121IO1020VDD19VSS18T3CK17SDI116SDO1Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.825.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829E=6.00mm · Pitch e=0.65mmD=6.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 6.00mm × 6.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RA5I/OMultiplexed I/O & Peripheral Pin RA5 (General)
2VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
3VREF-AnalogMultiplexed I/O & Peripheral Pin VREF- (General)
4ULPWUI/OMultiplexed I/O & Peripheral Pin ULPWU (General)
5U2RXI/OMultiplexed I/O & Peripheral Pin U2RX (General)
6U1RXI/OMultiplexed I/O & Peripheral Pin U1RX (General)
7RA2I/OMultiplexed I/O & Peripheral Pin RA2 (General)
8RA3I/OMultiplexed I/O & Peripheral Pin RA3 (General)
9U2RTSI/OMultiplexed I/O & Peripheral Pin U2RTS (General)
10U2CTSI/OMultiplexed I/O & Peripheral Pin U2CTS (General)
11U1TXI/OMultiplexed I/O & Peripheral Pin U1TX (General)
12U1CTSI/OMultiplexed I/O & Peripheral Pin U1CTS (General)
13U1RTSI/OMultiplexed I/O & Peripheral Pin U1RTS (General)
14RA6I/OMultiplexed I/O & Peripheral Pin RA6 (General)
15SS2I/OMultiplexed I/O & Peripheral Pin SS2 (General)
16SDO1I/OMultiplexed I/O & Peripheral Pin SDO1 (General)
17SDI1I/OMultiplexed I/O & Peripheral Pin SDI1 (General)
18T3CKI/OMultiplexed I/O & Peripheral Pin T3CK (General)
19VSSGNDGround Reference Pin (VSS)
20VDDPowerPower Supply Input (VDD — 1.8V to 3.6V)
21IO10I/OGPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0
22IO11I/OGPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID
23IO12I/OGPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK
24Vss/AVssGNDGround Reference Pin (Vss/AVss)
25Vdd/AVddPowerPower Supply Input (Vdd/AVdd — 1.8V to 3.6V)
26#MCLR/VPP/RA5I/OMultiplexed I/O & Peripheral Pin #MCLR/VPP/RA5 (General)
27IO47I/OGPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF
28IO33I/OGPIO33 / FSPIHD / SUBSPIHD / SPIIO4
29EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 RA5
I/O
Multiplexed I/O & Peripheral Pin RA5 (General)
Design note: Signal terminal RA5 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA5. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC24F32KA302-I/ML (MICROCHIP · QFN-28-EP(6x6))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC24F32KA302-I/ML (QFN-28-EP(6x6)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC24F32KA302-I/ML (QFN-28-EP(6x6)) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC24F32KA302-I/ML (QFN-28-EP(6x6)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC24F32KA302-I/ML (QFN-28-EP(6x6)) - 4. Package Dimensions (D×E×A)
QFN-28-EP(6x6) · 6.00×6.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC24F32KA302-I/ML (QFN-28-EP(6x6)) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC24F32KA302-I/ML (QFN-28-EP(6x6)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for PIC24F32KA30
P15 · p15_fig011540×2026px
PIC24F32KA302-I/ML (QFN-28-EP(6x6)) — FIGURE 1-1: PIC24FV32KA304 FAMILY GENERAL BLOCK DIAGRAM
FIGURE 1-1: PIC24FV32KA304 FAMILY GENERAL BLOCK DIAGRAM
P24 · p24_fig01867×977px
PIC24F32KA302-I/ML (QFN-28-EP(6x6)) — FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS
FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS
P27 · p27_fig01867×1876px
PIC24F32KA302-I/ML (QFN-28-EP(6x6)) — FIGURE 2-5: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT
FIGURE 2-5: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT
P232 · p232_fig01924×832px
PIC24F32KA302-I/ML (QFN-28-EP(6x6)) — FIGURE 25-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT
FIGURE 25-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT
P232 · p232_fig02977×660px
PIC24F32KA302-I/ML (QFN-28-EP(6x6)) — FIGURE 25-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT
FIGURE 25-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT
P233 · p233_fig011256×977px
PIC24F32KA302-I/ML (QFN-28-EP(6x6)) — FIGURE 25-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION
FIGURE 25-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION
P233 · p233_fig01P233
PIC24F32KA302-I/ML (QFN-28-EP(6x6)) — Datasheet Page 233 (p233_fig01)
Datasheet Page 233 (p233_fig01)
P344 · p344_fig011778×2733px
PIC24F32KA302-I/ML (QFN-28-EP(6x6)) — PIC24FV32KA304 FAMILY | DS30009995E-page 344  2011-2017 Microchip Technology Inc. | Microchip Technology Drawing C04-103D Sheet 2 of 2 | For the most current package drawings, please see the Microchip Packaging Specification located at htt
PIC24FV32KA304 FAMILY | DS30009995E-page 344  2011-2017 Microchip Technology Inc. | Microchip Technology Drawing C04-103D Sheet 2 of 2 | For the most current package drawings, please see the Microchip Packaging Specification located at htt
P344 · p344_fig01P344
PIC24F32KA302-I/ML (QFN-28-EP(6x6)) — Datasheet Page 344 (p344_fig01)
Datasheet Page 344 (p344_fig01)
P345 · p345_fig011778×2521px
PIC24F32KA302-I/ML (QFN-28-EP(6x6)) — PIC24FV32KA304 FAMILY
PIC24FV32KA304 FAMILY
P345 · p345_fig01P345
PIC24F32KA302-I/ML (QFN-28-EP(6x6)) — Datasheet Page 345 (p345_fig01)
Datasheet Page 345 (p345_fig01)
P348 · p348_fig011778×2733px
PIC24F32KA302-I/ML (QFN-28-EP(6x6)) — PIC24FV32KA304 FAMILY | DS30009995E-page 348  2011-2017 Microchip Technology Inc. | RECOMMENDED LAND PATTERN | 44-Lead Plastic Thin Quad Flatpack (PT) - 10X10X1 mm Body, 2.00 mm Footprint [TQFP] | SILK SCREEN | 1 2 | 44 C1 | E | G | Y1 | X
PIC24FV32KA304 FAMILY | DS30009995E-page 348  2011-2017 Microchip Technology Inc. | RECOMMENDED LAND PATTERN | 44-Lead Plastic Thin Quad Flatpack (PT) - 10X10X1 mm Body, 2.00 mm Footprint [TQFP] | SILK SCREEN | 1 2 | 44 C1 | E | G | Y1 | X
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (PIC24F32KA302-I/ML)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC24F32KA302-I/ML (QFN-28-EP(6x6)) is a 28-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V to 3.6V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, PWM, IrDA, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V to 3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 6.00 × 1.00 mm (A1=0.03 mm)
Package family: QFN (QFN-28-EP(6x6))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, PWM, IrDA, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteEPAD 4.70×4.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-28-EP(6x6))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.65mm
Pad Size (W × L)Level B
0.36 × 0.85 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-28-EP(6x6)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC24F32KA302-I/ML (QFN-28-EP(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC24F32KA302-I/ML (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the PIC24F32KA302-I/ML is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 1.8V to 3.6V. Key pins include: 1 (RA5: Multiplexed I/O & Peripheral Pin RA5 (General)), 2 (VREF+: Multiplexed I/O & Peripheral Pin VREF+ (General)), 3 (VREF-: Multiplexed I/O & Peripheral Pin VREF- (General)), 4 (ULPWU: Multiplexed I/O & Peripheral Pin ULPWU (General)), 5 (U2RX: Multiplexed I/O & Peripheral Pin U2RX (General)), 6 (U1RX: Multiplexed I/O & Peripheral Pin U1RX (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC24F32KA302-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC24F32KA302-I/ML (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC24F32KA302-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC24F32KA302-I/ML (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & PIC24F32KA30 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RA5Digital_IOSignal terminal RA5 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA5. Supported peripheral buses: General.
2VREF+AnalogSignal terminal VREF+ (Analog, 1.8V to 3.6V domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
3VREF-AnalogSignal terminal VREF- (Analog, 1.8V to 3.6V domain). Multiplexed alternate functions: VREF-. Supported peripheral buses: General.
4ULPWUDigital_IOSignal terminal ULPWU (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ULPWU. Supported peripheral buses: General.
5U2RXDigital_IOSignal terminal U2RX (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: U2RX. Supported peripheral buses: General.
6U1RXDigital_IOSignal terminal U1RX (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: U1RX. Supported peripheral buses: General.
7RA2Digital_IOSignal terminal RA2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA2. Supported peripheral buses: General.
8RA3Digital_IOSignal terminal RA3 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA3. Supported peripheral buses: General.
9U2RTSDigital_IOSignal terminal U2RTS (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: U2RTS. Supported peripheral buses: General.
10U2CTSDigital_IOSignal terminal U2CTS (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: U2CTS. Supported peripheral buses: General.
11U1TXDigital_IOSignal terminal U1TX (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: U1TX. Supported peripheral buses: General.
12U1CTSDigital_IOSignal terminal U1CTS (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: U1CTS. Supported peripheral buses: General.
13U1RTSDigital_IOSignal terminal U1RTS (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: U1RTS. Supported peripheral buses: General.
14RA6Digital_IOSignal terminal RA6 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA6. Supported peripheral buses: General.
15SS2Digital_IOSignal terminal SS2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: SS2. Supported peripheral buses: General.
16SDO1Digital_IOSignal terminal SDO1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: SDO1. Supported peripheral buses: General.
17SDI1Digital_IOSignal terminal SDI1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: SDI1. Supported peripheral buses: General.
18T3CKDigital_IOSignal terminal T3CK (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: T3CK. Supported peripheral buses: General.
19VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
20VDDPower_InPrimary positive power supply input (VDD) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
21IO10Digital_IOGPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0
22IO11Digital_IOGPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID
23IO12Digital_IOGPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK
24Vss/AVssGND0V electrical ground return terminal (Vss/AVss) for internal core logic, I/O drivers, and analog sub-blocks.
25Vdd/AVddPower_InPrimary positive power supply input (Vdd/AVdd) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
26#MCLR/VPP/RA5Digital_IOSignal terminal #MCLR/VPP/RA5 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: #MCLR/VPP/RA5. Supported peripheral buses: General.
27IO47Digital_IOGPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF
28IO33Digital_IOGPIO33 / FSPIHD / SUBSPIHD / SPIIO4
29EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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