SOP-16 · 16P
Synchronized Pinout (Symbol / 2D / 3D) (16/16)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | IO1 | I/O | General Purpose Digital I/O Pin IO1 |
| 2 | IO2 | I/O | General Purpose Digital I/O Pin IO2 |
| 3 | 3V3 | Power | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | P1.6/MISO/RXD1/TIN4 | I/O | Multiplexed I/O & Peripheral Pin P1.6/MISO/RXD1/TIN4 (UART, SPI) |
| 5 | P1.7/SCK/TXD1/TIN5 | I/O | Multiplexed I/O & Peripheral Pin P1.7/SCK/TXD1/TIN5 (UART, SPI) |
| 6 | RST/T2EX_/CAP2_ | I/O | Multiplexed I/O & Peripheral Pin RST/T2EX_/CAP2_ (General) |
| 7 | P3.1/PWM2_/TXD | I/O | Multiplexed I/O & Peripheral Pin P3.1/PWM2_/TXD (UART, PWM) |
| 8 | P3.0/PWM1_/RXD | I/O | Multiplexed I/O & Peripheral Pin P3.0/PWM1_/RXD (UART, PWM) |
| 9 | IO4 | I/O | GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3 |
| 10 | P3.3/INT1 | I/O | Multiplexed I/O & Peripheral Pin P3.3/INT1 (General) |
| 11 | P3.4/PWM2/RXD1_/T0 | I/O | Multiplexed I/O & Peripheral Pin P3.4/PWM2/RXD1_/T0 (UART, PWM) |
| 12 | P3.6/UDP | I/O | Multiplexed I/O & Peripheral Pin P3.6/UDP (General) |
| 13 | P3.7/UDM | I/O | Multiplexed I/O & Peripheral Pin P3.7/UDM (General) |
| 14 | GND/VSS | GND | Ground Reference Pin (GND/VSS) |
| 15 | VCC/VDD | Power | Power Supply Input (VCC/VDD — 3.3V / 5.0V Standard Logic) |
| 16 | V33 | Power | Power Supply Input (V33 — 3.3V / 5.0V Standard Logic) |
PIN 1 IO1
I/OGeneral Purpose Digital I/O Pin IO1
Design note: 3.3V logic domain (3.6V absolute max), 40mA max drive current.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 12 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (16 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SOP-16 · 3.90×9.90mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (16 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for CH554
P1 · p01_fig011684×868px
P2 · p02_fig011865×1645px
P2 · p02_fig01P2
P18 · p18_fig011757×2025px
P18 · p18_fig01P18
P22 · p22_fig011757×433px
P23 · p23_fig011664×915px
P37 · p37_fig011757×2277px
P37 · p37_fig021496×347px
P53 · p53_fig011757×2440px
P54 · p54_fig011757×2224px
P54 · p54_fig01P54
Technical Specifications & Part Details (CH554G)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH554G (SOP-16) is a 16-pin standard electronic & interconnect component featuring a 9.90 × 3.90 × 1.50 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, ADC, PWM interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
6MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
9.90 × 3.90 × 1.50 mm (A1=0.15 mm)
Package family: SOP (SOP-16)
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, ADC, PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol16 auto-grouped pins
IPC-7351B Land Pattern16 pads · Pitch 1.27mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH554 (2)
Mechanical Dimensions & Land Pattern (SOP-16)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
9.90 × 3.90 mm
Height (A) & Pitch (e)IPC-7351B
A=1.50mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.55 mm
Pins / Total PadsTopology
16P / 16Pad (DUAL_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit SOP-16 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH554G (SOP-16)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH554G (SOP-16)?
Manufactured by WCH, the CH554G is housed in a SOP-16 package with 16 pins and a 1.27 mm lead pitch. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (P1.6/MISO/RXD1/TIN4: Multiplexed I/O & Peripheral Pin P1.6/MISO/RXD1/TIN4 (UART, SPI)), 5 (P1.7/SCK/TXD1/TIN5: Multiplexed I/O & Peripheral Pin P1.7/SCK/TXD1/TIN5 (UART, SPI)), 6 (RST/T2EX_/CAP2_: Multiplexed I/O & Peripheral Pin RST/T2EX_/CAP2_ (General)).
What are the IPC-7351B PCB Footprint dimensions for CH554G?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH554G (SOP-16) has a nominal body envelope of 3.90 × 9.90 mm, pitch e = 1.27 mm, and 16 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH554G?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH554G (WCH, SOP-16) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (16 pins) & CH554 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | IO1 | Digital_IO | General Purpose Digital I/O Pin IO1 |
| 2 | IO2 | Digital_IO | General Purpose Digital I/O Pin IO2 |
| 3 | 3V3 | Power_In | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | P1.6/MISO/RXD1/TIN4 | Digital_IO | Signal terminal P1.6/MISO/RXD1/TIN4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.6/MISO/RXD1/TIN4. Supported peripheral buses: UART, SPI. |
| 5 | P1.7/SCK/TXD1/TIN5 | Digital_IO | Signal terminal P1.7/SCK/TXD1/TIN5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.7/SCK/TXD1/TIN5. Supported peripheral buses: UART, SPI. |
| 6 | RST/T2EX_/CAP2_ | Digital_IO | Signal terminal RST/T2EX_/CAP2_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST/T2EX_/CAP2_. Supported peripheral buses: General. |
| 7 | P3.1/PWM2_/TXD | Digital_IO | Signal terminal P3.1/PWM2_/TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.1/PWM2_/TXD. Supported peripheral buses: UART, PWM. |
| 8 | P3.0/PWM1_/RXD | Digital_IO | Signal terminal P3.0/PWM1_/RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.0/PWM1_/RXD. Supported peripheral buses: UART, PWM. |
| 9 | IO4 | Digital_IO | GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3 |
| 10 | P3.3/INT1 | Digital_IO | Signal terminal P3.3/INT1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.3/INT1. Supported peripheral buses: General. |
| 11 | P3.4/PWM2/RXD1_/T0 | Digital_IO | Signal terminal P3.4/PWM2/RXD1_/T0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.4/PWM2/RXD1_/T0. Supported peripheral buses: UART, PWM. |
| 12 | P3.6/UDP | Digital_IO | Signal terminal P3.6/UDP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.6/UDP. Supported peripheral buses: General. |
| 13 | P3.7/UDM | Digital_IO | Signal terminal P3.7/UDM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.7/UDM. Supported peripheral buses: General. |
| 14 | GND/VSS | GND | 0V electrical ground return terminal (GND/VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 15 | VCC/VDD | Power_In | Primary positive power supply input (VCC/VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 16 | V33 | Power_In | Primary positive power supply input (V33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |