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CH32L103K8U6 (QFN-32(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32L103K8U6

WCHID: C22472334QFN-32(4x4) · 33 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32L103K8U6 (QFN-32(4x4))1VDD2PC14/OSC32IN3PC15/OSC32OU4OSC_IN/PD05OSC_OUT/PD16PA0/WKUP/ADC7PA1/ADC18PA2/ADC29PA3/ADC310PA4/ADC411PA5/ADC512PA6/ADC613PA7/ADC714PB0/ADC815PB1/ADC916PB2/BOOT117PB1533EP32PB831BOOT0/PB930PB7/CC229PB6/CC128PB527PB426PB325PA1524PA14/SWCLK23PA13/SWDIO22PA12/UDP21PA11/UDM20PA1019PA918PA8Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.827.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233E=4.00mm · Pitch e=0.40mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDDPowerPower Supply Input (VDD — 1.8V~3.6V)
2PC14/OSC32INI/OMultiplexed I/O & Peripheral Pin PC14/OSC32IN (RTC/CLK)
3PC15/OSC32OUTI/OMultiplexed I/O & Peripheral Pin PC15/OSC32OUT (RTC/CLK)
4OSC_IN/PD0I/OMultiplexed I/O & Peripheral Pin OSC_IN/PD0 (RTC/CLK)
5OSC_OUT/PD1I/OMultiplexed I/O & Peripheral Pin OSC_OUT/PD1 (RTC/CLK)
6PA0/WKUP/ADC0I/OMultiplexed I/O & Peripheral Pin PA0/WKUP/ADC0 (ADC)
7PA1/ADC1I/OMultiplexed I/O & Peripheral Pin PA1/ADC1 (ADC)
8PA2/ADC2I/OMultiplexed I/O & Peripheral Pin PA2/ADC2 (ADC)
9PA3/ADC3I/OMultiplexed I/O & Peripheral Pin PA3/ADC3 (ADC)
10PA4/ADC4I/OMultiplexed I/O & Peripheral Pin PA4/ADC4 (ADC)
11PA5/ADC5I/OMultiplexed I/O & Peripheral Pin PA5/ADC5 (ADC)
12PA6/ADC6I/OMultiplexed I/O & Peripheral Pin PA6/ADC6 (ADC)
13PA7/ADC7I/OMultiplexed I/O & Peripheral Pin PA7/ADC7 (ADC)
14PB0/ADC8I/OMultiplexed I/O & Peripheral Pin PB0/ADC8 (ADC)
15PB1/ADC9I/OMultiplexed I/O & Peripheral Pin PB1/ADC9 (ADC)
16PB2/BOOT1I/OMultiplexed I/O & Peripheral Pin PB2/BOOT1 (General)
17PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
18PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
19PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
20PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
21PA11/UDMI/OMultiplexed I/O & Peripheral Pin PA11/UDM (General)
22PA12/UDPI/OMultiplexed I/O & Peripheral Pin PA12/UDP (General)
23PA13/SWDIOI/OMultiplexed I/O & Peripheral Pin PA13/SWDIO (SWD/JTAG)
24PA14/SWCLKI/OMultiplexed I/O & Peripheral Pin PA14/SWCLK (SWD/JTAG)
25PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
26PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
27PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
28PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
29PB6/CC1I/OMultiplexed I/O & Peripheral Pin PB6/CC1 (General)
30PB7/CC2I/OMultiplexed I/O & Peripheral Pin PB7/CC2 (General)
31BOOT0/PB9I/OMultiplexed I/O & Peripheral Pin BOOT0/PB9 (General)
32PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
33EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 VDD
Power
Power Supply Input (VDD — 1.8V~3.6V)
Design note: Primary positive power supply input (VDD) operating in the 1.8V~3.6V domain (Max rating: 3.6V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32L103K8U6 (WCH · QFN-32(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32L103K8U6 (QFN-32(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32L103K8U6 (QFN-32(4x4)) - 2. Standard Pinout (Top View)
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32L103K8U6 (QFN-32(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32L103K8U6 (QFN-32(4x4)) - 4. Package Dimensions (D×E×A)
QFN-32(4x4) · 4.00×4.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32L103K8U6 (QFN-32(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32L103K8U6 (QFN-32(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH32L103
P54 · p54_fig01EXACT PACKAGE
CH32L103K8U6 (QFN-32(4x4)) — CH32L103/M103 数据手册 https://wch.cn
CH32L103/M103 数据手册 https://wch.cn
P13 · p13_fig011239×2201px
CH32L103K8U6 (QFN-32(4x4)) — V2.1 11
V2.1 11
P13 · p13_fig01P13
CH32L103K8U6 (QFN-32(4x4)) — Datasheet Page 13 (p13_fig01)
Datasheet Page 13 (p13_fig01)
P15 · p15_fig011138×751px
CH32L103K8U6 (QFN-32(4x4)) — T:TIME_ (T1CH3:TIM1_CH3、T1CH1N:TIM1_CH1N、T1BK:TIM1_BKIN) OPA:OPA_ (OPAP4:OPA_P4、OPAN4:OPA_N4、OPAO2:OPA_O2) UDP:USBDP UDM:USBDM
T:TIME_ (T1CH3:TIM1_CH3、T1CH1N:TIM1_CH1N、T1BK:TIM1_BKIN) OPA:OPA_ (OPAP4:OPA_P4、OPAN4:OPA_N4、OPAO2:OPA_O2) UDP:USBDP UDM:USBDM
P16 · p16_fig011770×2440px
CH32L103K8U6 (QFN-32(4x4)) — V2.1 14
V2.1 14
P37 · p37_fig011961×1379px
CH32L103K8U6 (QFN-32(4x4)) — V2.1 35
V2.1 35

Technical Specifications & Part Details (CH32L103K8U6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH32L103K8U6 (QFN-32(4x4)) is a 32-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V~3.6V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V~3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
25MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-32(4x4))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2/BOOT1, BOOT0/PB9): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol33 auto-grouped pins
OK
IPC-7351B Land Pattern33 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 2.70×2.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-32(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-32(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32L103K8U6 (QFN-32(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32L103K8U6 (QFN-32(4x4))?

Manufactured by WCH, the CH32L103K8U6 is housed in a QFN-32(4x4) package with 33 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.8V~3.6V. Key pins include: 1 (VDD: Power Supply Input (VDD — 1.8V~3.6V)), 2 (PC14/OSC32IN: Multiplexed I/O & Peripheral Pin PC14/OSC32IN (RTC/CLK)), 3 (PC15/OSC32OUT: Multiplexed I/O & Peripheral Pin PC15/OSC32OUT (RTC/CLK)), 4 (OSC_IN/PD0: Multiplexed I/O & Peripheral Pin OSC_IN/PD0 (RTC/CLK)), 5 (OSC_OUT/PD1: Multiplexed I/O & Peripheral Pin OSC_OUT/PD1 (RTC/CLK)), 6 (PA0/WKUP/ADC0: Multiplexed I/O & Peripheral Pin PA0/WKUP/ADC0 (ADC)).

What are the IPC-7351B PCB Footprint dimensions for CH32L103K8U6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32L103K8U6 (QFN-32(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.40 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 2.70 × 2.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32L103K8U6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32L103K8U6 (WCH, QFN-32(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & CH32L103 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDDPower_InPrimary positive power supply input (VDD) operating in the 1.8V~3.6V domain (Max rating: 3.6V).
2PC14/OSC32INDigital_IOSignal terminal PC14/OSC32IN (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PC14/OSC32IN. Supported peripheral buses: RTC/CLK.
3PC15/OSC32OUTDigital_IOSignal terminal PC15/OSC32OUT (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PC15/OSC32OUT. Supported peripheral buses: RTC/CLK.
4OSC_IN/PD0Digital_IOSignal terminal OSC_IN/PD0 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: OSC_IN/PD0. Supported peripheral buses: RTC/CLK.
5OSC_OUT/PD1Digital_IOSignal terminal OSC_OUT/PD1 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: OSC_OUT/PD1. Supported peripheral buses: RTC/CLK.
6PA0/WKUP/ADC0AnalogSignal terminal PA0/WKUP/ADC0 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA0/WKUP/ADC0. Supported peripheral buses: ADC.
7PA1/ADC1AnalogSignal terminal PA1/ADC1 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA1/ADC1. Supported peripheral buses: ADC.
8PA2/ADC2AnalogSignal terminal PA2/ADC2 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA2/ADC2. Supported peripheral buses: ADC.
9PA3/ADC3AnalogSignal terminal PA3/ADC3 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA3/ADC3. Supported peripheral buses: ADC.
10PA4/ADC4AnalogSignal terminal PA4/ADC4 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA4/ADC4. Supported peripheral buses: ADC.
11PA5/ADC5AnalogSignal terminal PA5/ADC5 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA5/ADC5. Supported peripheral buses: ADC.
12PA6/ADC6AnalogSignal terminal PA6/ADC6 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA6/ADC6. Supported peripheral buses: ADC.
13PA7/ADC7AnalogSignal terminal PA7/ADC7 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA7/ADC7. Supported peripheral buses: ADC.
14PB0/ADC8AnalogSignal terminal PB0/ADC8 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB0/ADC8. Supported peripheral buses: ADC.
15PB1/ADC9AnalogSignal terminal PB1/ADC9 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB1/ADC9. Supported peripheral buses: ADC.
16PB2/BOOT1Digital_IOSignal terminal PB2/BOOT1 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB2/BOOT1. Supported peripheral buses: General.
17PB15Digital_IOSignal terminal PB15 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
18PA8Digital_IOSignal terminal PA8 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
19PA9Digital_IOSignal terminal PA9 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
20PA10Digital_IOSignal terminal PA10 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
21PA11/UDMDigital_IOSignal terminal PA11/UDM (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA11/UDM. Supported peripheral buses: General.
22PA12/UDPDigital_IOSignal terminal PA12/UDP (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA12/UDP. Supported peripheral buses: General.
23PA13/SWDIODigital_IOSignal terminal PA13/SWDIO (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA13/SWDIO. Supported peripheral buses: SWD/JTAG.
24PA14/SWCLKDigital_IOSignal terminal PA14/SWCLK (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA14/SWCLK. Supported peripheral buses: SWD/JTAG.
25PA15Digital_IOSignal terminal PA15 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
26PB3Digital_IOSignal terminal PB3 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
27PB4Digital_IOSignal terminal PB4 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
28PB5Digital_IOSignal terminal PB5 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
29PB6/CC1Digital_IOSignal terminal PB6/CC1 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB6/CC1. Supported peripheral buses: General.
30PB7/CC2Digital_IOSignal terminal PB7/CC2 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB7/CC2. Supported peripheral buses: General.
31BOOT0/PB9Digital_IOSignal terminal BOOT0/PB9 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: BOOT0/PB9. Supported peripheral buses: General.
32PB8Digital_IOSignal terminal PB8 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
33EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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