LX1688CPW (TSSOP-24) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of LX1688CPW (TSSOP-24)?

Manufactured by MICROCHIP, the LX1688CPW is housed in a TSSOP-24 package with 24 pins and a 0.65 mm lead pitch. Key pins include: 1 (AOUT: Multiplexed I/O & Peripheral Pin AOUT (General)), 2 (VSS_P: Ground Reference Pin (VSS_P)), 3 (VSS: Ground Reference Pin (VSS)), 4 (BEPOL: Multiplexed I/O & Peripheral Pin BEPOL (General)), 5 (BRITE: Multiplexed I/O & Peripheral Pin BRITE (General)), 6 (CPOR: Multiplexed I/O & Peripheral Pin CPOR (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for LX1688CPW?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), LX1688CPW (TSSOP-24) has a nominal body envelope of 4.40 × 7.80 mm, pitch e = 0.65 mm, and 24 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for LX1688CPW?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for LX1688CPW (MICROCHIP, TSSOP-24) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 4.40mm × 7.80mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (24/24)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	AOUT	I/O	Multiplexed I/O & Peripheral Pin AOUT (General)
2	VSS_P	GND	Ground Reference Pin (VSS_P)
3	VSS	GND	Ground Reference Pin (VSS)
4	BEPOL	I/O	Multiplexed I/O & Peripheral Pin BEPOL (General)
5	BRITE	I/O	Multiplexed I/O & Peripheral Pin BRITE (General)
6	CPOR	I/O	Multiplexed I/O & Peripheral Pin CPOR (General)
7	ENABLE	I/O	Multiplexed I/O & Peripheral Pin ENABLE (General)
8	I_R	I/O	Multiplexed I/O & Peripheral Pin I_R (General)
9	CPWM1	I/O	Multiplexed I/O & Peripheral Pin CPWM1 (General)
10	CPWM2	I/O	Multiplexed I/O & Peripheral Pin CPWM2 (General)
11	RMP_RST	I/O	Multiplexed I/O & Peripheral Pin RMP_RST (General)
12	PHA_SYNC	I/O	Multiplexed I/O & Peripheral Pin PHA_SYNC (General)
13	FAULT	I/O	Multiplexed I/O & Peripheral Pin FAULT (General)
14	SLAVE	I/O	Multiplexed I/O & Peripheral Pin SLAVE (General)
15	VSNS	I/O	Multiplexed I/O & Peripheral Pin VSNS (General)
16	VCOMP	I/O	Multiplexed I/O & Peripheral Pin VCOMP (General)
17	ICOMP	I/O	Multiplexed I/O & Peripheral Pin ICOMP (General)
18	ISNS	I/O	Multiplexed I/O & Peripheral Pin ISNS (General)
19	OLSNS	I/O	Multiplexed I/O & Peripheral Pin OLSNS (General)
20	TRI_C	I/O	Multiplexed I/O & Peripheral Pin TRI_C (General)
21	VDDSW	Power	Power Supply Input (VDDSW — 3.3V / 5.0V Standard Logic)
22	VDD	Power	Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
23	VDD_P	Power	Power Supply Input (VDD_P — 3.3V / 5.0V Standard Logic)
24	BOUT	I/O	Multiplexed I/O & Peripheral Pin BOUT (General)

PIN 1 AOUT

I/O

Multiplexed I/O & Peripheral Pin AOUT (General)

Design note: Signal terminal AOUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AOUT. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

LX1688CPW (TSSOP-24) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

LX1688CPW (TSSOP-24) - 2. Standard Pinout (Top View)

True package pinout (24 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

LX1688CPW (TSSOP-24) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

LX1688CPW (TSSOP-24) - 4. Package Dimensions (D×E×A)

TSSOP-24 · 4.40×7.80mm · Pitch 0.65mmExpand ›

5. Recommended Land PatternLAND PATTERN

LX1688CPW (TSSOP-24) - 5. Recommended Land Pattern

IPC-7351B Footprint (24 Pads)Expand ›

6. Application SchematicSCHEMATIC

LX1688CPW (TSSOP-24) - 6. Application Schematic

Typical Application SchematicExpand ›

Technical Specifications & Part Details (LX1688CPW)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:LX1688CPW (TSSOP-24) is a 24-pin standard electronic & interconnect component featuring a 7.80 × 4.40 × 1.20 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V ~ 5.5V (Theo Datasheet)

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

DC / Broadband Passive

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

7.80 × 4.40 × 1.20 mm (A1=0.10 mm)

Package family: TSSOP (TSSOP-24)

Pin Count & Lead PitchN / e

24 Pins | Pitch e = 0.65 mm (25.6 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

Standard I/O / Passive

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol24 auto-grouped pins

IPC-7351B Land Pattern24 pads · Pitch 0.65mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TSSOP-24)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

7.80 × 4.40 mm

Height (A) & Pitch (e)IPC-7351B

A=1.20mm · e=0.65mm

Pad Size (W × L)Level B

0.42 × 1.45 mm

Pins / Total PadsTopology

24P / 24Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit TSSOP-24	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — LX1688CPW (TSSOP-24)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of LX1688CPW (TSSOP-24)?

Manufactured by MICROCHIP, the LX1688CPW is housed in a TSSOP-24 package with 24 pins and a 0.65 mm lead pitch. Key pins include: 1 (AOUT: Multiplexed I/O & Peripheral Pin AOUT (General)), 2 (VSS_P: Ground Reference Pin (VSS_P)), 3 (VSS: Ground Reference Pin (VSS)), 4 (BEPOL: Multiplexed I/O & Peripheral Pin BEPOL (General)), 5 (BRITE: Multiplexed I/O & Peripheral Pin BRITE (General)), 6 (CPOR: Multiplexed I/O & Peripheral Pin CPOR (General)).

What are the IPC-7351B PCB Footprint dimensions for LX1688CPW?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), LX1688CPW (TSSOP-24) has a nominal body envelope of 4.40 × 7.80 mm, pitch e = 0.65 mm, and 24 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for LX1688CPW?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for LX1688CPW (MICROCHIP, TSSOP-24) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (24 pins) & LX1688 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	AOUT	Digital_IO	Signal terminal AOUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AOUT. Supported peripheral buses: General.
2	VSS_P	GND	0V electrical ground return terminal (VSS_P) for internal core logic, I/O drivers, and analog sub-blocks.
3	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
4	BEPOL	Digital_IO	Signal terminal BEPOL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BEPOL. Supported peripheral buses: General.
5	BRITE	Digital_IO	Signal terminal BRITE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BRITE. Supported peripheral buses: General.
6	CPOR	Digital_IO	Signal terminal CPOR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CPOR. Supported peripheral buses: General.
7	ENABLE	Digital_IO	Signal terminal ENABLE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ENABLE. Supported peripheral buses: General.
8	I_R	Digital_IO	Signal terminal I_R (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I_R. Supported peripheral buses: General.
9	CPWM1	Digital_IO	Signal terminal CPWM1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CPWM1. Supported peripheral buses: General.
10	CPWM2	Digital_IO	Signal terminal CPWM2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CPWM2. Supported peripheral buses: General.
11	RMP_RST	Digital_IO	Signal terminal RMP_RST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RMP_RST. Supported peripheral buses: General.
12	PHA_SYNC	Digital_IO	Signal terminal PHA_SYNC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PHA_SYNC. Supported peripheral buses: General.
13	FAULT	Digital_IO	Signal terminal FAULT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: FAULT. Supported peripheral buses: General.
14	SLAVE	Digital_IO	Signal terminal SLAVE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SLAVE. Supported peripheral buses: General.
15	VSNS	Digital_IO	Signal terminal VSNS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSNS. Supported peripheral buses: General.
16	VCOMP	Digital_IO	Signal terminal VCOMP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCOMP. Supported peripheral buses: General.
17	ICOMP	Digital_IO	Signal terminal ICOMP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ICOMP. Supported peripheral buses: General.
18	ISNS	Digital_IO	Signal terminal ISNS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ISNS. Supported peripheral buses: General.
19	OLSNS	Digital_IO	Signal terminal OLSNS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OLSNS. Supported peripheral buses: General.
20	TRI_C	Digital_IO	Signal terminal TRI_C (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TRI_C. Supported peripheral buses: General.
21	VDDSW	Power_In	Primary positive power supply input (VDDSW) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
22	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
23	VDD_P	Power_In	Primary positive power supply input (VDD_P) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
24	BOUT	Digital_IO	Signal terminal BOUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BOUT. Supported peripheral buses: General.

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