dsPIC33EP64GP502T-I/SS (SSOP-28-208mil) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of dsPIC33EP64GP502T-I/SS (SSOP-28-208mil)?

Manufactured by MICROCHIP, the dsPIC33EP64GP502T-I/SS is housed in a SSOP-28-208mil package with 28 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 3.0V to 3.6V. Key pins include: 1 (MCLR#: Multiplexed I/O & Peripheral Pin MCLR# (General)), 2 (AN0/OA2OUT/RA0: Multiplexed I/O & Peripheral Pin AN0/OA2OUT/RA0 (General)), 3 (AN1/C2IN1+/RA1: Multiplexed I/O & Peripheral Pin AN1/C2IN1+/RA1 (General)), 4 (NC: No Connect (Leave Floating)), 5 (IO2: GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1), 6 (IO3: GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)).

Q: What are the IPC-7351B PCB Footprint dimensions for dsPIC33EP64GP502T-I/SS?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), dsPIC33EP64GP502T-I/SS (SSOP-28-208mil) has a nominal body envelope of 5.30 × 10.20 mm, pitch e = 0.65 mm, and 28 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for dsPIC33EP64GP502T-I/SS?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for dsPIC33EP64GP502T-I/SS (MICROCHIP, SSOP-28-208mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 5.30mm × 10.20mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (28/28)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	MCLR#	I/O	Multiplexed I/O & Peripheral Pin MCLR# (General)
2	AN0/OA2OUT/RA0	I/O	Multiplexed I/O & Peripheral Pin AN0/OA2OUT/RA0 (General)
3	AN1/C2IN1+/RA1	I/O	Multiplexed I/O & Peripheral Pin AN1/C2IN1+/RA1 (General)
4	NC	NC	No Connect (Leave Floating)
5	IO2	I/O	GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1
6	IO3	I/O	GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)
7	NC	NC	No Connect (Leave Floating)
8	VSS	GND	Ground Reference Pin (VSS)
9	OSC1/CLKI/RA2	I/O	Multiplexed I/O & Peripheral Pin OSC1/CLKI/RA2 (RTC/CLK)
10	OSC2/CLKO/RA3	I/O	Multiplexed I/O & Peripheral Pin OSC2/CLKO/RA3 (RTC/CLK)
11	FLT32/RP36/RB4	I/O	Multiplexed I/O & Peripheral Pin FLT32/RP36/RB4 (General)
12	CVREF2O/RP20/T1CK/RA4	Analog	Multiplexed I/O & Peripheral Pin CVREF2O/RP20/T1CK/RA4 (General)
13	VDD	Power	Power Supply Input (VDD — 3.0V to 3.6V)
14	PGED2/ASDA2/RP37/RB5	I/O	Multiplexed I/O & Peripheral Pin PGED2/ASDA2/RP37/RB5 (General)
15	PGEC2/ASCL2/RP38/RB6	I/O	Multiplexed I/O & Peripheral Pin PGEC2/ASCL2/RP38/RB6 (General)
16	SCK1/RP39/INT0/RB7	I/O	Multiplexed I/O & Peripheral Pin SCK1/RP39/INT0/RB7 (SPI)
17	IO8	I/O	GPIO8 / RTC_GPIO8 / TOUCH8 / ADC1_CH7 / SUBSPICS1
18	IO19	I/O	GPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8
19	VSS	GND	Ground Reference Pin (VSS)
20	VCAP	I/O	Multiplexed I/O & Peripheral Pin VCAP (General)
21	TDO/RP42/PWM3H/RB10	I/O	Multiplexed I/O & Peripheral Pin TDO/RP42/PWM3H/RB10 (PWM)
22	TDI/RP43/PWM3L/RB11	I/O	Multiplexed I/O & Peripheral Pin TDI/RP43/PWM3L/RB11 (PWM)
23	RPI44/PWM2H/RB12	I/O	Multiplexed I/O & Peripheral Pin RPI44/PWM2H/RB12 (PWM)
24	RPI45/PWM2L/CTPLS/RB13	I/O	Multiplexed I/O & Peripheral Pin RPI45/PWM2L/CTPLS/RB13 (PWM)
25	RPI46/PWM1H/T3CK/RB14	I/O	Multiplexed I/O & Peripheral Pin RPI46/PWM1H/T3CK/RB14 (PWM)
26	RPI47/PWM1L/T5CK/RB15	I/O	Multiplexed I/O & Peripheral Pin RPI47/PWM1L/T5CK/RB15 (PWM)
27	AVSS	GND	Ground Reference Pin (AVSS)
28	AVDD	Power	Power Supply Input (AVDD — 3.0V to 3.6V)

PIN 1 MCLR#

I/O

Multiplexed I/O & Peripheral Pin MCLR# (General)

Design note: Signal terminal MCLR# (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: MCLR#. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

dsPIC33EP64GP502T-I/SS (SSOP-28-208mil) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

dsPIC33EP64GP502T-I/SS (SSOP-28-208mil) - 2. Standard Pinout (Top View)

True package pinout (28 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

dsPIC33EP64GP502T-I/SS (SSOP-28-208mil) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

dsPIC33EP64GP502T-I/SS (SSOP-28-208mil) - 4. Package Dimensions (D×E×A)

SSOP-28-208mil · 5.30×10.20mm · Pitch 0.65mmExpand ›

5. Recommended Land PatternLAND PATTERN

dsPIC33EP64GP502T-I/SS (SSOP-28-208mil) - 5. Recommended Land Pattern

IPC-7351B Footprint (28 Pads)Expand ›

6. Application SchematicSCHEMATIC

dsPIC33EP64GP502T-I/SS (SSOP-28-208mil) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)

Showing 1–10 of 10 uncropped original figures for DSPIC33EP64G

P1 · p01_fig01376×201px

16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, Op Amps and Advanced Analog

P27 · p27_fig011777×1658px

FIGURE 1-1: dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X BLOCK DIAGRAM

P34 · p34_fig011298×980px

FIGURE 2-4: BOOST CONVERTER IMPLEMENTATION

P36 · p36_fig011471×1006px

FIGURE 2-7: INTERLEAVED PFC

P36 · p36_fig021162×699px

FIGURE 2-8: BEMF VOLTAGE MEASURED USING THE ADC MODULE

P36 · p36_fig02P36

Datasheet Page 36 (p36_fig02)

P121 · p121_fig011777×980px

FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS

P500 · p500_fig011778×2529px

dsPIC33EP64GP502T-I/SS (SSOP-28-208mil) — DS70000657J-page 500  2011-2020 Microchip Technology Inc. | RECOMMENDED LAND PATTERN | Dimension Limits | Units | C2 | Center Pad Width | Contact Pad Spacing | Center Pad Length | Contact Pitch | Y2 X2 | 3.80 3.80 | MILLIMETERS | 0.40 BSC

P500 · p500_fig01P500

Datasheet Page 500 (p500_fig01)

P509 · p509_fig01All Packages in PDF

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X

Technical Specifications & Part Details (dsPIC33EP64GP502T-I/SS)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:dsPIC33EP64GP502T-I/SS (SSOP-28-208mil) is a 28-pin standard electronic & interconnect component featuring a 10.20 × 5.30 × 1.85 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 3.0V to 3.6V supply operation across -40°C to +85°C with integrated UART, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

3.0V to 3.6V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to +85°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

140 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

10.20 × 5.30 × 1.85 mm (A1=0.15 mm)

Package family: TSSOP (SSOP-28-208mil)

Pin Count & Lead PitchN / e

28 Pins | Pitch e = 0.65 mm (25.6 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

UART, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol28 auto-grouped pins

IPC-7351B Land Pattern28 pads · Pitch 0.65mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SSOP-28-208mil)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

10.20 × 5.30 mm

Height (A) & Pitch (e)IPC-7351B

A=1.85mm · e=0.65mm

Pad Size (W × L)Level B

0.42 × 1.60 mm

Pins / Total PadsTopology

28P / 28Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit SSOP-28-208mil	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — dsPIC33EP64GP502T-I/SS (SSOP-28-208mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of dsPIC33EP64GP502T-I/SS (SSOP-28-208mil)?

Manufactured by MICROCHIP, the dsPIC33EP64GP502T-I/SS is housed in a SSOP-28-208mil package with 28 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 3.0V to 3.6V. Key pins include: 1 (MCLR#: Multiplexed I/O & Peripheral Pin MCLR# (General)), 2 (AN0/OA2OUT/RA0: Multiplexed I/O & Peripheral Pin AN0/OA2OUT/RA0 (General)), 3 (AN1/C2IN1+/RA1: Multiplexed I/O & Peripheral Pin AN1/C2IN1+/RA1 (General)), 4 (NC: No Connect (Leave Floating)), 5 (IO2: GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1), 6 (IO3: GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)).

What are the IPC-7351B PCB Footprint dimensions for dsPIC33EP64GP502T-I/SS?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), dsPIC33EP64GP502T-I/SS (SSOP-28-208mil) has a nominal body envelope of 5.30 × 10.20 mm, pitch e = 0.65 mm, and 28 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for dsPIC33EP64GP502T-I/SS?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for dsPIC33EP64GP502T-I/SS (MICROCHIP, SSOP-28-208mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (28 pins) & DSPIC33EP64G Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	MCLR#	Digital_IO	Signal terminal MCLR# (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: MCLR#. Supported peripheral buses: General.
2	AN0/OA2OUT/RA0	Digital_IO	Signal terminal AN0/OA2OUT/RA0 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AN0/OA2OUT/RA0. Supported peripheral buses: General.
3	AN1/C2IN1+/RA1	Digital_IO	Signal terminal AN1/C2IN1+/RA1 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AN1/C2IN1+/RA1. Supported peripheral buses: General.
4	NC	No_Connect	No Connect (Leave Floating)
5	IO2	Digital_IO	GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1
6	IO3	Digital_IO	GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)
7	NC	No_Connect	No Connect (Leave Floating)
8	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
9	OSC1/CLKI/RA2	Digital_IO	Signal terminal OSC1/CLKI/RA2 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: OSC1/CLKI/RA2. Supported peripheral buses: RTC/CLK.
10	OSC2/CLKO/RA3	Digital_IO	Signal terminal OSC2/CLKO/RA3 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: OSC2/CLKO/RA3. Supported peripheral buses: RTC/CLK.
11	FLT32/RP36/RB4	Digital_IO	Signal terminal FLT32/RP36/RB4 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: FLT32/RP36/RB4. Supported peripheral buses: General.
12	CVREF2O/RP20/T1CK/RA4	Analog	Signal terminal CVREF2O/RP20/T1CK/RA4 (Analog, 3.0V to 3.6V domain). Multiplexed alternate functions: CVREF2O/RP20/T1CK/RA4. Supported peripheral buses: General.
13	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
14	PGED2/ASDA2/RP37/RB5	Digital_IO	Signal terminal PGED2/ASDA2/RP37/RB5 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PGED2/ASDA2/RP37/RB5. Supported peripheral buses: General.
15	PGEC2/ASCL2/RP38/RB6	Digital_IO	Signal terminal PGEC2/ASCL2/RP38/RB6 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PGEC2/ASCL2/RP38/RB6. Supported peripheral buses: General.
16	SCK1/RP39/INT0/RB7	Digital_IO	Signal terminal SCK1/RP39/INT0/RB7 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SCK1/RP39/INT0/RB7. Supported peripheral buses: SPI.
17	IO8	Digital_IO	GPIO8 / RTC_GPIO8 / TOUCH8 / ADC1_CH7 / SUBSPICS1
18	IO19	Digital_IO	GPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8
19	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
20	VCAP	Digital_IO	Signal terminal VCAP (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
21	TDO/RP42/PWM3H/RB10	Digital_IO	Signal terminal TDO/RP42/PWM3H/RB10 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TDO/RP42/PWM3H/RB10. Supported peripheral buses: PWM.
22	TDI/RP43/PWM3L/RB11	Digital_IO	Signal terminal TDI/RP43/PWM3L/RB11 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TDI/RP43/PWM3L/RB11. Supported peripheral buses: PWM.
23	RPI44/PWM2H/RB12	Digital_IO	Signal terminal RPI44/PWM2H/RB12 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RPI44/PWM2H/RB12. Supported peripheral buses: PWM.
24	RPI45/PWM2L/CTPLS/RB13	Digital_IO	Signal terminal RPI45/PWM2L/CTPLS/RB13 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RPI45/PWM2L/CTPLS/RB13. Supported peripheral buses: PWM.
25	RPI46/PWM1H/T3CK/RB14	Digital_IO	Signal terminal RPI46/PWM1H/T3CK/RB14 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RPI46/PWM1H/T3CK/RB14. Supported peripheral buses: PWM.
26	RPI47/PWM1L/T5CK/RB15	Digital_IO	Signal terminal RPI47/PWM1L/T5CK/RB15 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RPI47/PWM1L/T5CK/RB15. Supported peripheral buses: PWM.
27	AVSS	GND	0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
28	AVDD	Power_In	Primary positive power supply input (AVDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).

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