MIC23356YFT-TR (PTQFN-16(2.5x2.5)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of MIC23356YFT-TR (PTQFN-16(2.5x2.5))?

Manufactured by MICROCHIP, the MIC23356YFT-TR is housed in a PTQFN-16(2.5x2.5) package with 11 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.4V to 5.5V. Key pins include: 1 (SW: Multiplexed I/O & Peripheral Pin SW (General)), 3 (PGND: Ground Reference Pin (PGND)), 4 (PV IN: Multiplexed I/O & Peripheral Pin PV IN (General)), 6 (SV IN: Multiplexed I/O & Peripheral Pin SV IN (General)), 7 (SCL: Multiplexed I/O & Peripheral Pin SCL (I2C)), 8 (SDA: Multiplexed I/O & Peripheral Pin SDA (I2C)).

Q: What are the IPC-7351B PCB Footprint dimensions for MIC23356YFT-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MIC23356YFT-TR (PTQFN-16(2.5x2.5)) has a nominal body envelope of 2.50 × 2.50 mm, pitch e = 0.50 mm, and 11 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MIC23356YFT-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MIC23356YFT-TR (MICROCHIP, PTQFN-16(2.5x2.5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 2.50mm × 2.50mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (11/11)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	SW	I/O	Multiplexed I/O & Peripheral Pin SW (General)
3	PGND	GND	Ground Reference Pin (PGND)
4	PV IN	I/O	Multiplexed I/O & Peripheral Pin PV IN (General)
6	SV IN	I/O	Multiplexed I/O & Peripheral Pin SV IN (General)
7	SCL	I/O	Multiplexed I/O & Peripheral Pin SCL (I2C)
8	SDA	I/O	Multiplexed I/O & Peripheral Pin SDA (I2C)
9	EN	I	System Enable & Hardware Reset (EN)
10	PG	I/O	Multiplexed I/O & Peripheral Pin PG (General)
11	V OUT	I/O	Multiplexed I/O & Peripheral Pin V OUT (General)
12	A GND	GND	Ground Reference Pin (A GND)
13	PGND	GND	Ground Reference Pin (PGND)

PIN 1 SW

I/O

Multiplexed I/O & Peripheral Pin SW (General)

Design note: SwitchNode

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

MIC23356YFT-TR (PTQFN-16(2.5x2.5)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

MIC23356YFT-TR (PTQFN-16(2.5x2.5)) - 2. Standard Pinout (Top View)

True package pinout (11 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

MIC23356YFT-TR (PTQFN-16(2.5x2.5)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

MIC23356YFT-TR (PTQFN-16(2.5x2.5)) - 4. Package Dimensions (D×E×A)

PTQFN-16(2.5x2.5) · 2.50×2.50mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

MIC23356YFT-TR (PTQFN-16(2.5x2.5)) - 5. Recommended Land Pattern

IPC-7351B Footprint (11 Pads)Expand ›

6. Application SchematicSCHEMATIC

MIC23356YFT-TR (PTQFN-16(2.5x2.5)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)

Showing 1–12 of 12 uncropped original figures for MIC23356

P1 · p01_fig01376×200px

3A, Step-Down Converter with HyperLight Load™ and I2C Interface

P2 · p02_fig011518×965px

Typical Application

P2 · p02_fig021182×880px

Ordering Information

P2 · p02_fig02P2

Datasheet Page 2 (p02_fig02)

P3 · p03_fig011777×1586px

MIC23356

P19 · p19_fig01867×797px

EQUATION 5-3:

P19 · p19_fig02867×292px

The RMS inductor current is used to calculate the I2R losses in the inductor.

P30 · p30_fig011399×863px

MIC23356YFT-TR (PTQFN-16(2.5x2.5)) — 16-Lead FTQFN 2.5 mm x 2.5 mm Example | 23356 | 7256 WNNN | Part Number Marking Marking Code | MIC23356YFT XXXX 23356 | MIC23356-FAYFT XXXX 356FA | MIC23356-HAYFT XXXX 356HA | MIC23356-SAYFT XXXX 356SA

P30 · p30_fig02412×248px

16-Lead FTQFN 2.5 mm x 2.5 mm Example

P30 · p30_fig03408×246px

16-Lead FTQFN 2.5 mm x 2.5 mm Example

P30 · p30_fig041361×615px

 2019 Microchip Technology Inc. DS20006130A-page 30

P30 · p30_fig02P30

Datasheet Page 30 (p30_fig02)

Technical Specifications & Part Details (MIC23356YFT-TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:MIC23356YFT-TR (PTQFN-16(2.5x2.5)) is a 10-pin standard electronic & interconnect component featuring a 2.50 × 2.50 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.4V to 5.5V supply operation across -40°C to +125°C with integrated I2C, DAC interfaces.

Operating Supply VoltageV_CC / V_DD

2.4V to 5.5V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to +125°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

3.4 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

2.50 × 2.50 × 0.85 mm (A1=0.03 mm)

Package family: QFN (PTQFN-16(2.5x2.5))

Pin Count & Lead PitchN / e

10 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

I2C, DAC

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol11 auto-grouped pins

IPC-7351B Land Pattern11 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PTQFN-16(2.5x2.5))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

2.50 × 2.50 mm

Height (A) & Pitch (e)IPC-7351B

A=0.85mm · e=0.50mm

Pad Size (W × L)Level B

0.25 × 0.50 mm

Pins / Total PadsTopology

11P / 11Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit PTQFN-16(2.5x2.5)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MIC23356YFT-TR (PTQFN-16(2.5x2.5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MIC23356YFT-TR (PTQFN-16(2.5x2.5))?

Manufactured by MICROCHIP, the MIC23356YFT-TR is housed in a PTQFN-16(2.5x2.5) package with 11 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.4V to 5.5V. Key pins include: 1 (SW: Multiplexed I/O & Peripheral Pin SW (General)), 3 (PGND: Ground Reference Pin (PGND)), 4 (PV IN: Multiplexed I/O & Peripheral Pin PV IN (General)), 6 (SV IN: Multiplexed I/O & Peripheral Pin SV IN (General)), 7 (SCL: Multiplexed I/O & Peripheral Pin SCL (I2C)), 8 (SDA: Multiplexed I/O & Peripheral Pin SDA (I2C)).

What are the IPC-7351B PCB Footprint dimensions for MIC23356YFT-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MIC23356YFT-TR (PTQFN-16(2.5x2.5)) has a nominal body envelope of 2.50 × 2.50 mm, pitch e = 0.50 mm, and 11 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MIC23356YFT-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MIC23356YFT-TR (MICROCHIP, PTQFN-16(2.5x2.5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (11 pins) & MIC23356 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	SW	Digital_IO	Signal terminal SW (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: SW. Supported peripheral buses: General.
3	PGND	GND	0V electrical ground return terminal (PGND) for internal core logic, I/O drivers, and analog sub-blocks.
4	PV IN	Digital_IO	Signal terminal PV IN (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: PV IN. Supported peripheral buses: General.
6	SV IN	Digital_IO	Signal terminal SV IN (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: SV IN. Supported peripheral buses: General.
7	SCL	Digital_IO	Signal terminal SCL (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
8	SDA	Digital_IO	Signal terminal SDA (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
9	EN	Digital_IO	Chip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset.
10	PG	Open_Drain	Signal terminal PG (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: PG. Supported peripheral buses: General.
11	V OUT	Digital_IO	Signal terminal V OUT (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: V OUT. Supported peripheral buses: General.
12	A GND	GND	0V electrical ground return terminal (A GND) for internal core logic, I/O drivers, and analog sub-blocks.
13	PGND	GND	0V electrical ground return terminal (PGND) for internal core logic, I/O drivers, and analog sub-blocks.

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