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CH32M030K9U7 (QFN-32(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32M030K9U7

WCHID: C53145393QFN-32(4x4) · 33 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32M030K9U7 (QFN-32(4x4))1HVCP2PB14/LO3CAP13VDD54PB7/HVOD5PC5/HVIO/CAP6VDD337VHV8PA0/CC1/A139PA1/CC2/A1410PA2/SWCK/CC311IO612PB0/UDP/CM3P13PB1/UDM/CM3P14PA6/ISINK1/C15PA7/ISINK2/C16PA8/ISN1/CM317ISP133GND32PB15/HVOD331PB13/HVOD230CAP229PB12/LO2CAP228PB11/HVOD127PB9/HVOD026PB8/LO025PB5/CM2P/A324PB4/V_DET/A123PA15/SCL_2/A22PA14/SDA_2/A21PA13/QII2/A120PA12/QII1/A119PA11/ISN2/A818PA10/ISP2Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.827.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233E=4.00mm · Pitch e=0.40mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1HVCPI/OMultiplexed I/O & Peripheral Pin HVCP (General)
2PB14/LO3CAP1I/OMultiplexed I/O & Peripheral Pin PB14/LO3CAP1 (General)
3VDD5PowerPower Supply Input (VDD5 — 3.3V / 5.0V Standard Logic)
4PB7/HVODI/OMultiplexed I/O & Peripheral Pin PB7/HVOD (General)
5PC5/HVIO/CAP1I/OMultiplexed I/O & Peripheral Pin PC5/HVIO/CAP1 (General)
6VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
7VHVI/OMultiplexed I/O & Peripheral Pin VHV (General)
8PA0/CC1/A13I/OMultiplexed I/O & Peripheral Pin PA0/CC1/A13 (General)
9PA1/CC2/A14I/OMultiplexed I/O & Peripheral Pin PA1/CC2/A14 (General)
10PA2/SWCK/CC3/SCL_/A15I/OMultiplexed I/O & Peripheral Pin PA2/SWCK/CC3/SCL_/A15 (I2C)
11IO6I/OGPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5
12PB0/UDP/CM3P1/A11I/OMultiplexed I/O & Peripheral Pin PB0/UDP/CM3P1/A11 (General)
13PB1/UDM/CM3P2/A12I/OMultiplexed I/O & Peripheral Pin PB1/UDM/CM3P2/A12 (General)
14PA6/ISINK1/CM3N1I/OMultiplexed I/O & Peripheral Pin PA6/ISINK1/CM3N1 (General)
15PA7/ISINK2/CM3N2/A2I/OMultiplexed I/O & Peripheral Pin PA7/ISINK2/CM3N2/A2 (General)
16PA8/ISN1/CM3O/A7I/OMultiplexed I/O & Peripheral Pin PA8/ISN1/CM3O/A7 (General)
17ISP1I/OMultiplexed I/O & Peripheral Pin ISP1 (General)
18PA10/ISP2I/OMultiplexed I/O & Peripheral Pin PA10/ISP2 (General)
19PA11/ISN2/A8I/OMultiplexed I/O & Peripheral Pin PA11/ISN2/A8 (General)
20PA12/QII1/A19I/OMultiplexed I/O & Peripheral Pin PA12/QII1/A19 (General)
21PA13/QII2/A18I/OMultiplexed I/O & Peripheral Pin PA13/QII2/A18 (General)
22PA14/SDA_2/A9I/OMultiplexed I/O & Peripheral Pin PA14/SDA_2/A9 (I2C)
23PA15/SCL_2/A10I/OMultiplexed I/O & Peripheral Pin PA15/SCL_2/A10 (I2C)
24PB4/V_DET/A17I/OMultiplexed I/O & Peripheral Pin PB4/V_DET/A17 (General)
25PB5/CM2P/A3I/OMultiplexed I/O & Peripheral Pin PB5/CM2P/A3 (General)
26PB8/LO0I/OMultiplexed I/O & Peripheral Pin PB8/LO0 (General)
27PB9/HVOD0I/OMultiplexed I/O & Peripheral Pin PB9/HVOD0 (General)
28PB11/HVOD1I/OMultiplexed I/O & Peripheral Pin PB11/HVOD1 (General)
29PB12/LO2CAP2I/OMultiplexed I/O & Peripheral Pin PB12/LO2CAP2 (General)
30CAP2I/OMultiplexed I/O & Peripheral Pin CAP2 (General)
31PB13/HVOD2I/OMultiplexed I/O & Peripheral Pin PB13/HVOD2 (General)
32PB15/HVOD3I/OMultiplexed I/O & Peripheral Pin PB15/HVOD3 (General)
33GNDGNDGround Reference Pin (GND)
PIN 1 HVCP
I/O
Multiplexed I/O & Peripheral Pin HVCP (General)
Design note: Signal terminal HVCP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVCP. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32M030K9U7 (WCH · QFN-32(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32M030K9U7 (QFN-32(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32M030K9U7 (QFN-32(4x4)) - 2. Standard Pinout (Top View)
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32M030K9U7 (QFN-32(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32M030K9U7 (QFN-32(4x4)) - 4. Package Dimensions (D×E×A)
QFN-32(4x4) · 4.00×4.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32M030K9U7 (QFN-32(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32M030K9U7 (QFN-32(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for CH32M030
P1 · p01_fig011004×957px
CH32M030K9U7 (QFN-32(4x4)) — PA12/QII1/A19 28
PA12/QII1/A19 28
P1 · p01_fig021104×1089px
CH32M030K9U7 (QFN-32(4x4)) — V1.2 1
V1.2 1
P1 · p01_fig01P1
CH32M030K9U7 (QFN-32(4x4)) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P6 · p06_fig011511×1755px
CH32M030K9U7 (QFN-32(4x4)) — 图2-1 内部升压模块结构图
图2-1 内部升压模块结构图
P6 · p06_fig01P6
CH32M030K9U7 (QFN-32(4x4)) — Datasheet Page 6 (p06_fig01)
Datasheet Page 6 (p06_fig01)
P7 · p07_fig011852×2623px
CH32M030K9U7 (QFN-32(4x4)) — V1.2 7
V1.2 7
P9 · p09_fig011370×1364px
CH32M030K9U7 (QFN-32(4x4)) — (一) 、建议C1=C2=C3=0.01uF～0.1uF，R1=1MΩ，R2、R3 可根据实际应用所需分压选择阻值。 (二) 、配置FLASH_CTLR2 寄存器的VDD8_SEL=00（默认值），VDD5=5V。 (三) 、开启HVCP 升压。
(一) 、建议C1=C2=C3=0.01uF～0.1uF，R1=1MΩ，R2、R3 可根据实际应用所需分压选择阻值。 (二) 、配置FLASH_CTLR2 寄存器的VDD8_SEL=00（默认值），VDD5=5V。 (三) 、开启HVCP 升压。

Technical Specifications & Part Details (CH32M030K9U7)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH32M030K9U7 (QFN-32(4x4)) is a 32-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated I2C interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-32(4x4))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol33 auto-grouped pins
OK
IPC-7351B Land Pattern33 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 2.56×2.56mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-32(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-32(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32M030K9U7 (QFN-32(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32M030K9U7 (QFN-32(4x4))?

Manufactured by WCH, the CH32M030K9U7 is housed in a QFN-32(4x4) package with 33 pins and a 0.40 mm lead pitch. Key pins include: 1 (HVCP: Multiplexed I/O & Peripheral Pin HVCP (General)), 2 (PB14/LO3CAP1: Multiplexed I/O & Peripheral Pin PB14/LO3CAP1 (General)), 3 (VDD5: Power Supply Input (VDD5 — 3.3V / 5.0V Standard Logic)), 4 (PB7/HVOD: Multiplexed I/O & Peripheral Pin PB7/HVOD (General)), 5 (PC5/HVIO/CAP1: Multiplexed I/O & Peripheral Pin PC5/HVIO/CAP1 (General)), 6 (VDD33: Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)).

What are the IPC-7351B PCB Footprint dimensions for CH32M030K9U7?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32M030K9U7 (QFN-32(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.40 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 2.56 × 2.56 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32M030K9U7?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32M030K9U7 (WCH, QFN-32(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & CH32M030 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1HVCPDigital_IOSignal terminal HVCP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVCP. Supported peripheral buses: General.
2PB14/LO3CAP1Digital_IOSignal terminal PB14/LO3CAP1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14/LO3CAP1. Supported peripheral buses: General.
3VDD5Power_InPrimary positive power supply input (VDD5) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4PB7/HVODDigital_IOSignal terminal PB7/HVOD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7/HVOD. Supported peripheral buses: General.
5PC5/HVIO/CAP1Digital_IOSignal terminal PC5/HVIO/CAP1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5/HVIO/CAP1. Supported peripheral buses: General.
6VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
7VHVDigital_IOSignal terminal VHV (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VHV. Supported peripheral buses: General.
8PA0/CC1/A13Digital_IOSignal terminal PA0/CC1/A13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0/CC1/A13. Supported peripheral buses: General.
9PA1/CC2/A14Digital_IOSignal terminal PA1/CC2/A14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1/CC2/A14. Supported peripheral buses: General.
10PA2/SWCK/CC3/SCL_/A15Digital_IOSignal terminal PA2/SWCK/CC3/SCL_/A15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2/SWCK/CC3/SCL_/A15. Supported peripheral buses: I2C.
11IO6Digital_IOGPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5
12PB0/UDP/CM3P1/A11Digital_IOSignal terminal PB0/UDP/CM3P1/A11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0/UDP/CM3P1/A11. Supported peripheral buses: General.
13PB1/UDM/CM3P2/A12Digital_IOSignal terminal PB1/UDM/CM3P2/A12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1/UDM/CM3P2/A12. Supported peripheral buses: General.
14PA6/ISINK1/CM3N1Digital_IOSignal terminal PA6/ISINK1/CM3N1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6/ISINK1/CM3N1. Supported peripheral buses: General.
15PA7/ISINK2/CM3N2/A2Digital_IOSignal terminal PA7/ISINK2/CM3N2/A2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7/ISINK2/CM3N2/A2. Supported peripheral buses: General.
16PA8/ISN1/CM3O/A7Digital_IOSignal terminal PA8/ISN1/CM3O/A7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8/ISN1/CM3O/A7. Supported peripheral buses: General.
17ISP1Digital_IOSignal terminal ISP1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ISP1. Supported peripheral buses: General.
18PA10/ISP2Digital_IOSignal terminal PA10/ISP2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10/ISP2. Supported peripheral buses: General.
19PA11/ISN2/A8Digital_IOSignal terminal PA11/ISN2/A8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11/ISN2/A8. Supported peripheral buses: General.
20PA12/QII1/A19Digital_IOSignal terminal PA12/QII1/A19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12/QII1/A19. Supported peripheral buses: General.
21PA13/QII2/A18Digital_IOSignal terminal PA13/QII2/A18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13/QII2/A18. Supported peripheral buses: General.
22PA14/SDA_2/A9Digital_IOSignal terminal PA14/SDA_2/A9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14/SDA_2/A9. Supported peripheral buses: I2C.
23PA15/SCL_2/A10Digital_IOSignal terminal PA15/SCL_2/A10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15/SCL_2/A10. Supported peripheral buses: I2C.
24PB4/V_DET/A17Digital_IOSignal terminal PB4/V_DET/A17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4/V_DET/A17. Supported peripheral buses: General.
25PB5/CM2P/A3Digital_IOSignal terminal PB5/CM2P/A3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5/CM2P/A3. Supported peripheral buses: General.
26PB8/LO0Digital_IOSignal terminal PB8/LO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8/LO0. Supported peripheral buses: General.
27PB9/HVOD0Digital_IOSignal terminal PB9/HVOD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9/HVOD0. Supported peripheral buses: General.
28PB11/HVOD1Digital_IOSignal terminal PB11/HVOD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11/HVOD1. Supported peripheral buses: General.
29PB12/LO2CAP2Digital_IOSignal terminal PB12/LO2CAP2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12/LO2CAP2. Supported peripheral buses: General.
30CAP2Digital_IOSignal terminal CAP2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CAP2. Supported peripheral buses: General.
31PB13/HVOD2Digital_IOSignal terminal PB13/HVOD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13/HVOD2. Supported peripheral buses: General.
32PB15/HVOD3Digital_IOSignal terminal PB15/HVOD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15/HVOD3. Supported peripheral buses: General.
33GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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