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STM32G061F8Y6TR (WLCSP-20) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32G061F8Y6TR

STID: C5270143WLCSP-20 · 20 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32G061F8Y6TR (WLCSP-20)A1PA12[PA10]A2PB6A3PB8A4PB9B1PA11[PA9]B2PA13B3PA15B4IOB4C1PA6C2PA3E4PF2NRST -E3PA2E2PA4E1PA8D4VSS/VSSAD3PA1D2PA5D1PA7C4VDD/VDDAC3PA0Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
A1A2A3A4B1B2B3B4C1C2C3C4D1D2D3D4E1E2E3E4E=2.00mm · Pitch e=0.40mmD=2.50mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 2.00mm × 2.50mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PA12[PA10]I/OMultiplexed I/O & Peripheral Pin PA12[PA10] (UART, SPI, ADC)
A2PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART)
A3PB8I/OMultiplexed I/O & Peripheral Pin PB8 (SPI)
A4PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI)
B1PA11[PA9]I/OMultiplexed I/O & Peripheral Pin PA11[PA9] (UART, SPI, I2C, ADC)
B2PA13I/OMultiplexed I/O & Peripheral Pin PA13 (ADC, SWD/JTAG)
B3PA15I/OMultiplexed I/O & Peripheral Pin PA15 (UART, SPI)
B4IOB4I/OGeneral Purpose Digital I/O Pin IOB4
C1PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC)
C2PA3I/OMultiplexed I/O & Peripheral Pin PA3 (SPI, PWM)
C3PA0I/OMultiplexed I/O & Peripheral Pin PA0 (SPI, ADC)
C4VDD/VDDAPowerPower Supply Input (VDD/VDDA — 3.3V VDD (Max 4.0V))
D1PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
D2PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC)
D3PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, SPI, PWM)
D4VSS/VSSAGNDGround Reference Pin (VSS/VSSA)
E1PA8I/OMultiplexed I/O & Peripheral Pin PA8 (SPI, RTC/CLK)
E2PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI, ADC, DAC, RTC/CLK)
E3PA2I/OMultiplexed I/O & Peripheral Pin PA2 (SPI, ADC, PWM)
E4PF2NRST -I/OMultiplexed I/O & Peripheral Pin PF2NRST - (RTC/CLK)
PIN A1 PA12[PA10]
I/O
Multiplexed I/O & Peripheral Pin PA12[PA10] (UART, SPI, ADC)
Design note: Alt: SPI1 MOSI/I2S1_SD_ , USART1_RTSDECK__ , TIM1_ETRI2SCKIN ,_ , COMP2_OUTI2C2SDA ,_ | Add: ADC_IN16
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 19 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32G061F8Y6TR (ST · WLCSP-20)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32G061F8Y6TR (WLCSP-20) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32G061F8Y6TR (WLCSP-20) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32G061F8Y6TR (WLCSP-20) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32G061F8Y6TR (WLCSP-20) - 4. Package Dimensions (D×E×A)
WLCSP-20 · 2.00×2.50mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32G061F8Y6TR (WLCSP-20) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32G061F8Y6TR (WLCSP-20) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (19 figures · Page 1/2)
Showing 1–12 of 19 uncropped original figures for STM32G061
P36 · p36_fig01EXACT PACKAGE
STM32G061F8Y6TR (WLCSP-20) — Figure 7. STM32G061GxU UFQFPN28 pinout Top view
Figure 7. STM32G061GxU UFQFPN28 pinout Top view
P36 · p36_fig02EXACT PACKAGE
STM32G061F8Y6TR (WLCSP-20) — Figure 8. STM32G061Fx TSSOP20 pinout
Figure 8. STM32G061Fx TSSOP20 pinout
P37 · p37_fig01EXACT PACKAGE
STM32G061F8Y6TR (WLCSP-20) — Figure 9. STM32G061FxY WLCSP20L pinout
Figure 9. STM32G061FxY WLCSP20L pinout
P104 · p104_fig01EXACT PACKAGE
STM32G061F8Y6TR (WLCSP-20) — Figure 33. WLCSP20 - Recommended footprint
Figure 33. WLCSP20 - Recommended footprint
P1 · p01_fig01883×534px
STM32G061F8Y6TR (WLCSP-20) — Arm® Cortex®-M0+ 32-bit MCU, up to 64 KB Flash, 18 KB RAM, 2x USART, timers, ADC, DAC, comm. I/Fs, AES, RNG, 1.7-3.6V | Datasheet - production data | UFQFPN48 | UFQFPN32 | UFQFPN28 | LQFP48 | LQFP32 | 7 × 7 mm | 5 × 5 mm | 4 × 4 mm | 7 × 7
Arm® Cortex®-M0+ 32-bit MCU, up to 64 KB Flash, 18 KB RAM, 2x USART, timers, ADC, DAC, comm. I/Fs, AES, RNG, 1.7-3.6V | Datasheet - production data | UFQFPN48 | UFQFPN32 | UFQFPN28 | LQFP48 | LQFP32 | 7 × 7 mm | 5 × 5 mm | 4 × 4 mm | 7 × 7
P34 · p34_fig011546×917px
STM32G061F8Y6TR (WLCSP-20) — Figure 3. STM32G061CxT LQFP48 pinout
Figure 3. STM32G061CxT LQFP48 pinout
P34 · p34_fig021546×903px
STM32G061F8Y6TR (WLCSP-20) — Figure 4. STM32G061CxU UFQFPN48 pinout
Figure 4. STM32G061CxU UFQFPN48 pinout
P34 · p34_fig03517×517px
STM32G061F8Y6TR (WLCSP-20) — Figure 4. STM32G061CxU UFQFPN48 pinout
Figure 4. STM32G061CxU UFQFPN48 pinout
P46 · p46_fig011548×1316px
STM32G061F8Y6TR (WLCSP-20) — Figure 12. Power supply scheme
Figure 12. Power supply scheme
P46 · p46_fig01P46
STM32G061F8Y6TR (WLCSP-20) — Datasheet Page 46 (p46_fig01)
Datasheet Page 46 (p46_fig01)
P65 · p65_fig011546×702px
STM32G061F8Y6TR (WLCSP-20) — Figure 17. Typical application with an 8 MHz crystal
Figure 17. Typical application with an 8 MHz crystal
P66 · p66_fig011546×701px
STM32G061F8Y6TR (WLCSP-20) — Figure 18. Typical application with a 32.768 kHz crystal
Figure 18. Typical application with a 32.768 kHz crystal
Page 1 / 2 (19 extracted figures)

Technical Specifications & Part Details (STM32G061F8Y6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32G061F8Y6TR (WLCSP-20) is a 20-pin embedded microcontroller unit (mcu) featuring a 2.50 × 2.00 × 0.56 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.62 V - 3.6 V supply operation across -40°C to 85°C with integrated UART, SPI, I2C, I2S, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.62 V - 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
64 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
17 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
2.50 × 2.00 × 0.56 mm (A1=0.18 mm)
Package family: WLCSP (WLCSP-20)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, I2S, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — STM32G061 (2)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (WLCSP-20)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
2.50 × 2.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.56mm · e=0.40mm
Pad Size (W × L)Level B
0.21 × 0.21 mm
Pins / Total PadsTopology
20P / 20Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-20
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32G061F8Y6TR (WLCSP-20)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32G061F8Y6TR (WLCSP-20)?

Manufactured by ST, the STM32G061F8Y6TR is housed in a WLCSP-20 package with 20 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.62 V - 3.6 V. Key pins include: A1 (PA12[PA10]: Multiplexed I/O & Peripheral Pin PA12[PA10] (UART, SPI, ADC)), A2 (PB6: Multiplexed I/O & Peripheral Pin PB6 (UART)), A3 (PB8: Multiplexed I/O & Peripheral Pin PB8 (SPI)), A4 (PB9: Multiplexed I/O & Peripheral Pin PB9 (SPI)), B1 (PA11[PA9]: Multiplexed I/O & Peripheral Pin PA11[PA9] (UART, SPI, I2C, ADC)), B2 (PA13: Multiplexed I/O & Peripheral Pin PA13 (ADC, SWD/JTAG)).

What are the IPC-7351B PCB Footprint dimensions for STM32G061F8Y6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32G061F8Y6TR (WLCSP-20) has a nominal body envelope of 2.00 × 2.50 mm, pitch e = 0.40 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32G061F8Y6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32G061F8Y6TR (ST, WLCSP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & STM32G061 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PA12[PA10]Digital_IOSignal terminal PA12[PA10] (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: UART, SPI, ADC.
A2PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART.
A3PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKTIM16CH1. Supported peripheral buses: SPI.
A4PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSSI2C1SDA. Supported peripheral buses: SPI.
B1PA11[PA9]Digital_IOSignal terminal PA11[PA9] (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, I2C2_SCL. Supported peripheral buses: UART, SPI, I2C, ADC.
B2PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: ADC, SWD/JTAG.
B3PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI.
B4IOB4Digital_IOGeneral Purpose Digital I/O Pin IOB4
C1PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC.
C2PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISOUSART2RX. Supported peripheral buses: SPI, PWM.
C3PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKUSART2CTS. Supported peripheral buses: SPI, ADC.
C4VDD/VDDAPower_InPrimary positive power supply input (VDD/VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D1PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
D2PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC.
D3PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, PWM.
D4VSS/VSSAGND0V electrical ground return terminal (VSS/VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
E1PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI, RTC/CLK.
E2PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI2_MOSITIM14CH1. Supported peripheral buses: SPI, ADC, DAC, RTC/CLK.
E3PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
E4PF2NRST -Digital_IOSignal terminal PF2NRST - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2NRST -. Supported peripheral buses: RTC/CLK.
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