SOP-8 · 8P
Synchronized Pinout (Symbol / 2D / 3D) (20/20)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | PD4 I/O/A PD4 | I/O | Multiplexed I/O & Peripheral Pin PD4 I/O/A PD4 (General) |
| 2 | PD5 I/O/A PD5 | I/O | Multiplexed I/O & Peripheral Pin PD5 I/O/A PD5 (General) |
| 3 | PD6 I/O/A PD6 | I/O | Multiplexed I/O & Peripheral Pin PD6 I/O/A PD6 (General) |
| 4 | PD7 I/O/A PD7 | I/O | Multiplexed I/O & Peripheral Pin PD7 I/O/A PD7 (General) |
| 5 | PA1 I/O/A PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 I/O/A PA1 (General) |
| 6 | PA2 I/O/A PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 I/O/A PA2 (General) |
| 7 | VSS | GND | Ground Reference Pin (VSS) |
| 8 | IO0 | I/O | GPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin) |
| 9 | VDD | Power | Power Supply Input (VDD — 2.7V~5.5V) |
| 10 | IO5 | I/O | GPIO5 / RTC_GPIO5 / TOUCH5 / ADC1_CH4 |
| 11 | PC1 I/O/FT PC1 | I/O | Multiplexed I/O & Peripheral Pin PC1 I/O/FT PC1 (SPI, I2C) |
| 12 | PC2 I/O/FT PC2 | I/O | Multiplexed I/O & Peripheral Pin PC2 I/O/FT PC2 (I2C) |
| 13 | PC3 I/O PC3 | I/O | Multiplexed I/O & Peripheral Pin PC3 I/O PC3 (General) |
| 14 | PC4 I/O/A PC4 | I/O | Multiplexed I/O & Peripheral Pin PC4 I/O/A PC4 (RTC/CLK) |
| 15 | PC5 I/O/FT PC5 | I/O | Multiplexed I/O & Peripheral Pin PC5 I/O/FT PC5 (SPI) |
| 16 | PC6 I/O/FT PC6 | I/O | Multiplexed I/O & Peripheral Pin PC6 I/O/FT PC6 (SPI) |
| 17 | PC7 I/O PC7 | I/O | Multiplexed I/O & Peripheral Pin PC7 I/O PC7 (SPI) |
| 18 | PD1 I/O/A PD1 | I/O | Multiplexed I/O & Peripheral Pin PD1 I/O/A PD1 (General) |
| 19 | PD2 I/O/A PD2 | I/O | Multiplexed I/O & Peripheral Pin PD2 I/O/A PD2 (General) |
| 20 | IO9 | I/O | GPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD |
PIN 1 PD4 I/O/A PD4
I/OMultiplexed I/O & Peripheral Pin PD4 I/O/A PD4 (General)
Design note: UCK/T2CH1ETR(1)/A7/OPO
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
TSSOP-20-175mil · 4.40×6.50mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH32V003
P28 · p28_fig01EXACT PACKAGE
P2 · p02_fig012644×2907px
P2 · p02_fig01P2
P9 · p09_fig011564×491px
P9 · p09_fig021242×1602px
P9 · p09_fig031541×453px
P9 · p09_fig041511×467px
P9 · p09_fig02P9
Technical Specifications & Part Details (CH32V003F4P6)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH32V003F4P6 (TSSOP-20-175mil) is a 20-pin embedded microcontroller unit (mcu) featuring a 6.50 × 4.40 × 1.20 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 2.7V~5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
2.7V~5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
25MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.50 × 4.40 × 1.20 mm (A1=0.00 mm)
Package family: TSSOP (TSSOP-20-175mil)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol20 auto-grouped pins
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH32V003 (4)
TSSOP-20-175mil · 20P
QFN-20(3X3) · 21P
- · 20P
Mechanical Dimensions & Land Pattern (TSSOP-20-175mil)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
6.50 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.45 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit TSSOP-20-175mil | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH32V003F4P6 (TSSOP-20-175mil)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH32V003F4P6 (TSSOP-20-175mil)?
Manufactured by WCH, the CH32V003F4P6 is housed in a TSSOP-20-175mil package with 20 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.7V~5.5V. Key pins include: 1 (PD4 I/O/A PD4: Multiplexed I/O & Peripheral Pin PD4 I/O/A PD4 (General)), 2 (PD5 I/O/A PD5: Multiplexed I/O & Peripheral Pin PD5 I/O/A PD5 (General)), 3 (PD6 I/O/A PD6: Multiplexed I/O & Peripheral Pin PD6 I/O/A PD6 (General)), 4 (PD7 I/O/A PD7: Multiplexed I/O & Peripheral Pin PD7 I/O/A PD7 (General)), 5 (PA1 I/O/A PA1: Multiplexed I/O & Peripheral Pin PA1 I/O/A PA1 (General)), 6 (PA2 I/O/A PA2: Multiplexed I/O & Peripheral Pin PA2 I/O/A PA2 (General)).
What are the IPC-7351B PCB Footprint dimensions for CH32V003F4P6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32V003F4P6 (TSSOP-20-175mil) has a nominal body envelope of 4.40 × 6.50 mm, pitch e = 0.65 mm, and 20 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32V003F4P6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32V003F4P6 (WCH, TSSOP-20-175mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (20 pins) & CH32V003 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PD4 I/O/A PD4 | Digital_IO | Signal terminal PD4 I/O/A PD4 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PD4 I/O/A PD4. Supported peripheral buses: General. |
| 2 | PD5 I/O/A PD5 | Digital_IO | Signal terminal PD5 I/O/A PD5 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PD5 I/O/A PD5. Supported peripheral buses: General. |
| 3 | PD6 I/O/A PD6 | Digital_IO | Signal terminal PD6 I/O/A PD6 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PD6 I/O/A PD6. Supported peripheral buses: General. |
| 4 | PD7 I/O/A PD7 | Digital_IO | Signal terminal PD7 I/O/A PD7 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PD7 I/O/A PD7. Supported peripheral buses: General. |
| 5 | PA1 I/O/A PA1 | Digital_IO | Signal terminal PA1 I/O/A PA1 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA1 I/O/A PA1. Supported peripheral buses: General. |
| 6 | PA2 I/O/A PA2 | Digital_IO | Signal terminal PA2 I/O/A PA2 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA2 I/O/A PA2. Supported peripheral buses: General. |
| 7 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 8 | IO0 | Digital_IO | GPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin) |
| 9 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 2.7V~5.5V domain (Max rating: 5.5V). |
| 10 | IO5 | Digital_IO | GPIO5 / RTC_GPIO5 / TOUCH5 / ADC1_CH4 |
| 11 | PC1 I/O/FT PC1 | Digital_IO | Signal terminal PC1 I/O/FT PC1 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC1 I/O/FT PC1. Supported peripheral buses: SPI, I2C. |
| 12 | PC2 I/O/FT PC2 | Digital_IO | Signal terminal PC2 I/O/FT PC2 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC2 I/O/FT PC2. Supported peripheral buses: I2C. |
| 13 | PC3 I/O PC3 | Digital_IO | Signal terminal PC3 I/O PC3 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC3 I/O PC3. Supported peripheral buses: General. |
| 14 | PC4 I/O/A PC4 | Digital_IO | Signal terminal PC4 I/O/A PC4 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC4 I/O/A PC4. Supported peripheral buses: RTC/CLK. |
| 15 | PC5 I/O/FT PC5 | Digital_IO | Signal terminal PC5 I/O/FT PC5 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC5 I/O/FT PC5. Supported peripheral buses: SPI. |
| 16 | PC6 I/O/FT PC6 | Digital_IO | Signal terminal PC6 I/O/FT PC6 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC6 I/O/FT PC6. Supported peripheral buses: SPI. |
| 17 | PC7 I/O PC7 | Digital_IO | Signal terminal PC7 I/O PC7 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC7 I/O PC7. Supported peripheral buses: SPI. |
| 18 | PD1 I/O/A PD1 | Digital_IO | Signal terminal PD1 I/O/A PD1 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PD1 I/O/A PD1. Supported peripheral buses: General. |
| 19 | PD2 I/O/A PD2 | Digital_IO | Signal terminal PD2 I/O/A PD2 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PD2 I/O/A PD2. Supported peripheral buses: General. |
| 20 | IO9 | Digital_IO | GPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD |