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CH543D (QFN-20(3x3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH543D

WCHID: C5183760QFN-20(3x3) · 21 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH543D (QFN-20(3x3))1VDD12/VHV2GND/VSS3VDD/V334NC5P3.2/INT0/A26P1.5/MOSI/PW7NC8P1.7/SCK/SDA9RST/T2EX_/CA10P3.1/TXD/PWM11P3.0/RXD/PWM21GND/VSS20P1.2/INT0_/A19P1.3/A11/CM18P3.7/DM/A917P3.6/DP/A816P3.5/T1/HVIO15P3.4/T0/PWM114P3.3/INT1/PW13P1.0/CC1/T2/12P1.1/CC2/T2EGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.220.315.210.25.10-5.1-10.2-15.2-20.3mm
2. 2D FOOTPRINT
123456789101112131415161718192021E=3.00mm · Pitch e=0.40mmD=3.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.00mm × 3.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (21/21)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDD12/VHVPowerPower Supply Input (VDD12/VHV — 3.3V / 5.0V Standard Logic)
2GND/VSSGNDGround Reference Pin (GND/VSS)
3VDD/V33PowerPower Supply Input (VDD/V33 — 3.3V / 5.0V Standard Logic)
4NCNCNo Connect (Leave Floating)
5P3.2/INT0/A2I/OMultiplexed I/O & Peripheral Pin P3.2/INT0/A2 (General)
6P1.5/MOSI/PWM0/A5I/OMultiplexed I/O & Peripheral Pin P1.5/MOSI/PWM0/A5 (SPI, PWM)
7NCNCNo Connect (Leave Floating)
8P1.7/SCK/SDA/TXD_/A7I/OMultiplexed I/O & Peripheral Pin P1.7/SCK/SDA/TXD_/A7 (UART, SPI, I2C)
9RST/T2EX_/CAP2_/A3/CPI/OMultiplexed I/O & Peripheral Pin RST/T2EX_/CAP2_/A3/CP (General)
10P3.1/TXD/PWM1_/SDA_I/OMultiplexed I/O & Peripheral Pin P3.1/TXD/PWM1_/SDA_ (UART, I2C, PWM)
11P3.0/RXD/PWM0_/SCL_I/OMultiplexed I/O & Peripheral Pin P3.0/RXD/PWM0_/SCL_ (UART, I2C, PWM)
12P1.1/CC2/T2EX/CAP2/A1I/OMultiplexed I/O & Peripheral Pin P1.1/CC2/T2EX/CAP2/A1 (General)
13P1.0/CC1/T2/CAP1/A0I/OMultiplexed I/O & Peripheral Pin P1.0/CC1/T2/CAP1/A0 (General)
14P3.3/INT1/PWM2_I/OMultiplexed I/O & Peripheral Pin P3.3/INT1/PWM2_ (PWM)
15P3.4/T0/PWM1I/OMultiplexed I/O & Peripheral Pin P3.4/T0/PWM1 (PWM)
16P3.5/T1/HVIOI/OMultiplexed I/O & Peripheral Pin P3.5/T1/HVIO (General)
17P3.6/DP/A8I/OMultiplexed I/O & Peripheral Pin P3.6/DP/A8 (General)
18P3.7/DM/A9I/OMultiplexed I/O & Peripheral Pin P3.7/DM/A9 (General)
19P1.3/A11/CMI/OMultiplexed I/O & Peripheral Pin P1.3/A11/CM (General)
20P1.2/INT0_/A10/COI/OMultiplexed I/O & Peripheral Pin P1.2/INT0_/A10/CO (General)
21GND/VSSGNDGround Reference Pin (GND/VSS)
PIN 1 VDD12/VHV
Power
Power Supply Input (VDD12/VHV — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VDD12/VHV) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH543D (WCH · QFN-20(3x3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH543D (QFN-20(3x3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH543D (QFN-20(3x3)) - 2. Standard Pinout (Top View)
True package pinout (21 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH543D (QFN-20(3x3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH543D (QFN-20(3x3)) - 4. Package Dimensions (D×E×A)
QFN-20(3x3) · 3.00×3.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH543D (QFN-20(3x3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (21 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH543D (QFN-20(3x3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for CH543
P73 · p73_fig01EXACT PACKAGE
CH543D (QFN-20(3x3)) — 20.1 TSSOP20 20.2 QFN20-3*3 #100 — #20 | ST oT [TT a CT [TT Hf iD oT [TT (a a CT [TT — Cor CTO i, Co [TT als _— 2 CT [TT] © Ey oO CT [TT = #10 COO TT #11 [ol rt _ 4.4 La J wo - S o 0.6
20.1 TSSOP20 20.2 QFN20-3*3 #100 — #20 | ST oT [TT a CT [TT Hf iD oT [TT (a a CT [TT — Cor CTO i, Co [TT als _— 2 CT [TT] © Ey oO CT [TT = #10 COO TT #11 [ol rt _ 4.4 La J wo - S o 0.6
P73 · p73_fig02EXACT PACKAGE
CH543D (QFN-20(3x3)) — 20.1 TSSOP20 20.2 QFN20-3*3 3.0+0.1 0.2+0. 05 LJ olLd ld ld LJ u u u UJ q Spe moO LS Ts 7“ 2 | i ie > 1.7+0.1 — a | Top View | L a > | Bottom View| @ =| jc ree) > CI > je #705 ms #A.>3 CT | PTF. oF. i } f ) | f a #1 | O04+0.05 #1 _~ re Ato.
20.1 TSSOP20 20.2 QFN20-3*3 3.0+0.1 0.2+0. 05 LJ olLd ld ld LJ u u u UJ q Spe moO LS Ts 7“ 2 | i ie > 1.7+0.1 — a | Top View | L a > | Bottom View| @ =| jc ree) > CI > je #705 ms #A.>3 CT | PTF. oF. i } f ) | f a #1 | O04+0.05 #1 _~ re Ato.
P1 · p01_fig011736×915px
CH543D (QFN-20(3x3)) — 下面为CH543 的内部框图，仅供参考。 Pins: GND VDD12 VDD RST P10~17 P30~37 | Internal Address & Data & DMA Bus 1T E8051 Core | PO Reset LV Reset | Watch-dog | Reset | iRAM 256B xRAM 256B | UART0 PWM0 ~PWM3 Timer2 Cap1~2 | USB host & device ADC tkey | Flash
下面为CH543 的内部框图，仅供参考。 Pins: GND VDD12 VDD RST P10~17 P30~37 | Internal Address & Data & DMA Bus 1T E8051 Core | PO Reset LV Reset | Watch-dog | Reset | iRAM 256B xRAM 256B | UART0 PWM0 ~PWM3 Timer2 Cap1~2 | USB host & device ADC tkey | Flash
P3 · p03_fig011971×2713px
CH543D (QFN-20(3x3)) — CH543 手册 3 | GND/VSS 2 | P3.6/DP/A8 17 | P3.7/DM/A9 18 | P1.5/MOSI/PWM0/A5 6 P1.6/MISO/SCL/RXD_/PWM2/A6 7 P1.7/SCK/SDA/TXD_/A7 8 RST/T2EX_/CAP2_/A3/CP 9 | P3.2/INT0/A2 5 P1.1/CC2/T2EX/CAP2/A1 12 | P3.1/TXD/PWM1_/SDA_ 10 | P3.0/RXD/PWM0_/SCL
CH543 手册 3 | GND/VSS 2 | P3.6/DP/A8 17 | P3.7/DM/A9 18 | P1.5/MOSI/PWM0/A5 6 P1.6/MISO/SCL/RXD_/PWM2/A6 7 P1.7/SCK/SDA/TXD_/A7 8 RST/T2EX_/CAP2_/A3/CP 9 | P3.2/INT0/A2 5 P1.1/CC2/T2EX/CAP2/A1 12 | P3.1/TXD/PWM1_/SDA_ 10 | P3.0/RXD/PWM0_/SCL
P17 · p17_fig011757×1384px
CH543D (QFN-20(3x3)) — 在电源上电或者系统复位后，CH543 默认处于运行状态。在性能满足要求的前提下，适当降低 系统主频可以降低运行时的功耗。当CH543 完全不需要运行时，可以设置PCON 中的PD 进入睡眠状 态，睡眠状态下可以选择通过USB、USB PD、UART0、I2C、SPI0 以及部分GPIO 进行外部唤醒。 7.2 电源和睡眠控制寄存器 表7.2.1 电源和睡眠控制寄存器列表 | 名称 地址 描述 复位值 | WDOG_COUNT FFh 看门狗计数寄存器 00h | POWER_
在电源上电或者系统复位后，CH543 默认处于运行状态。在性能满足要求的前提下，适当降低 系统主频可以降低运行时的功耗。当CH543 完全不需要运行时，可以设置PCON 中的PD 进入睡眠状 态，睡眠状态下可以选择通过USB、USB PD、UART0、I2C、SPI0 以及部分GPIO 进行外部唤醒。 7.2 电源和睡眠控制寄存器 表7.2.1 电源和睡眠控制寄存器列表 | 名称 地址 描述 复位值 | WDOG_COUNT FFh 看门狗计数寄存器 00h | POWER_
P22 · p22_fig011757×1455px
CH543D (QFN-20(3x3)) — CH543 手册 22 | 相应的中断服务程序后自动清零 | 4 bUART_2X RW | UART0 模块倍频模式： 0-使用Fsys 作为参考时钟，产生正常通讯波特率； 1-使用2 倍频的Fsys，产生两倍的通讯波特率 0 | 3 保留 RO 保留 0 | [2:0] MASK_SYS_CK_SEL RW 系统时钟频率选择，参考下表8.2.2 011b | 表8.2.2 系统主频选择表 | MASK_SYS_CK_SEL 系统主频Fsys Fsys 频率 说明 | 00
CH543 手册 22 | 相应的中断服务程序后自动清零 | 4 bUART_2X RW | UART0 模块倍频模式： 0-使用Fsys 作为参考时钟，产生正常通讯波特率； 1-使用2 倍频的Fsys，产生两倍的通讯波特率 0 | 3 保留 RO 保留 0 | [2:0] MASK_SYS_CK_SEL RW 系统时钟频率选择，参考下表8.2.2 011b | 表8.2.2 系统主频选择表 | MASK_SYS_CK_SEL 系统主频Fsys Fsys 频率 说明 | 00
P26 · p26_fig011757×414px
CH543D (QFN-20(3x3)) — 位 名称 访问 描述 复位值
位 名称 访问 描述 复位值
P47 · p47_fig011757×1764px
CH543D (QFN-20(3x3)) — 位 名称 访问 描述 复位值
位 名称 访问 描述 复位值
P47 · p47_fig021757×804px
CH543D (QFN-20(3x3)) — 注：采样时间为4 个参考时钟，Cs 指信号源并联电容值，Rs 指信号源串联内阻值。 对于RST 和两个内部ADC 通道，内阻大，需选择较慢的参考时钟，或者多采样几次，丢弃前值。 当P1.0/P1.1 输入模拟电压较高、接近VDD 时，需选择较慢的参考时钟，或者多采样几次。 ADC 模拟信号通道选择寄存器(ADC_CHAN)： | 位 名称 访问 描述 复位值 | [7:4] 保留 R0 保留 0000b | [3:0] MASK_ADC_CHAN RW 当bADC_EN=1
注：采样时间为4 个参考时钟，Cs 指信号源并联电容值，Rs 指信号源串联内阻值。 对于RST 和两个内部ADC 通道，内阻大，需选择较慢的参考时钟，或者多采样几次，丢弃前值。 当P1.0/P1.1 输入模拟电压较高、接近VDD 时，需选择较慢的参考时钟，或者多采样几次。 ADC 模拟信号通道选择寄存器(ADC_CHAN)： | 位 名称 访问 描述 复位值 | [7:4] 保留 R0 保留 0000b | [3:0] MASK_ADC_CHAN RW 当bADC_EN=1
P47 · p47_fig01P47
CH543D (QFN-20(3x3)) — Datasheet Page 47 (p47_fig01)
Datasheet Page 47 (p47_fig01)

Technical Specifications & Part Details (CH543D)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH543D (QFN-20(3x3)) is a 20-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, PWM interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
48MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-20(3x3))
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol21 auto-grouped pins
OK
IPC-7351B Land Pattern21 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 1.65×1.65mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-20(3x3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
21P / 21Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-20(3x3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH543D (QFN-20(3x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH543D (QFN-20(3x3))?

Manufactured by WCH, the CH543D is housed in a QFN-20(3x3) package with 21 pins and a 0.40 mm lead pitch. Key pins include: 1 (VDD12/VHV: Power Supply Input (VDD12/VHV — 3.3V / 5.0V Standard Logic)), 2 (GND/VSS: Ground Reference Pin (GND/VSS)), 3 (VDD/V33: Power Supply Input (VDD/V33 — 3.3V / 5.0V Standard Logic)), 4 (NC: No Connect (Leave Floating)), 5 (P3.2/INT0/A2: Multiplexed I/O & Peripheral Pin P3.2/INT0/A2 (General)), 6 (P1.5/MOSI/PWM0/A5: Multiplexed I/O & Peripheral Pin P1.5/MOSI/PWM0/A5 (SPI, PWM)).

What are the IPC-7351B PCB Footprint dimensions for CH543D?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH543D (QFN-20(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.40 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 1.65 × 1.65 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH543D?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH543D (WCH, QFN-20(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (21 pins) & CH543 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDD12/VHVPower_InPrimary positive power supply input (VDD12/VHV) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2GND/VSSGND0V electrical ground return terminal (GND/VSS) for internal core logic, I/O drivers, and analog sub-blocks.
3VDD/V33Power_InPrimary positive power supply input (VDD/V33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4NCNo_ConnectNo Connect (Leave Floating)
5P3.2/INT0/A2Digital_IOSignal terminal P3.2/INT0/A2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.2/INT0/A2. Supported peripheral buses: General.
6P1.5/MOSI/PWM0/A5Digital_IOSignal terminal P1.5/MOSI/PWM0/A5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.5/MOSI/PWM0/A5. Supported peripheral buses: SPI, PWM.
7NCNo_ConnectNo Connect (Leave Floating)
8P1.7/SCK/SDA/TXD_/A7Digital_IOSignal terminal P1.7/SCK/SDA/TXD_/A7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.7/SCK/SDA/TXD_/A7. Supported peripheral buses: UART, SPI, I2C.
9RST/T2EX_/CAP2_/A3/CPDigital_IOSignal terminal RST/T2EX_/CAP2_/A3/CP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST/T2EX_/CAP2_/A3/CP. Supported peripheral buses: General.
10P3.1/TXD/PWM1_/SDA_Digital_IOSignal terminal P3.1/TXD/PWM1_/SDA_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.1/TXD/PWM1_/SDA_. Supported peripheral buses: UART, I2C, PWM.
11P3.0/RXD/PWM0_/SCL_Digital_IOSignal terminal P3.0/RXD/PWM0_/SCL_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.0/RXD/PWM0_/SCL_. Supported peripheral buses: UART, I2C, PWM.
12P1.1/CC2/T2EX/CAP2/A1Digital_IOSignal terminal P1.1/CC2/T2EX/CAP2/A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.1/CC2/T2EX/CAP2/A1. Supported peripheral buses: General.
13P1.0/CC1/T2/CAP1/A0Digital_IOSignal terminal P1.0/CC1/T2/CAP1/A0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.0/CC1/T2/CAP1/A0. Supported peripheral buses: General.
14P3.3/INT1/PWM2_Digital_IOSignal terminal P3.3/INT1/PWM2_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.3/INT1/PWM2_. Supported peripheral buses: PWM.
15P3.4/T0/PWM1Digital_IOSignal terminal P3.4/T0/PWM1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.4/T0/PWM1. Supported peripheral buses: PWM.
16P3.5/T1/HVIODigital_IOSignal terminal P3.5/T1/HVIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.5/T1/HVIO. Supported peripheral buses: General.
17P3.6/DP/A8Digital_IOSignal terminal P3.6/DP/A8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.6/DP/A8. Supported peripheral buses: General.
18P3.7/DM/A9Digital_IOSignal terminal P3.7/DM/A9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.7/DM/A9. Supported peripheral buses: General.
19P1.3/A11/CMDigital_IOSignal terminal P1.3/A11/CM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.3/A11/CM. Supported peripheral buses: General.
20P1.2/INT0_/A10/CODigital_IOSignal terminal P1.2/INT0_/A10/CO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.2/INT0_/A10/CO. Supported peripheral buses: General.
21GND/VSSGND0V electrical ground return terminal (GND/VSS) for internal core logic, I/O drivers, and analog sub-blocks.
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