MCP4362-103E/ST (TSSOP-14) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of MCP4362-103E/ST (TSSOP-14)?

Manufactured by MICROCHIP, the MCP4362-103E/ST is housed in a TSSOP-14 package with 14 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.7V to 5.5V. Key pins include: 1 (P3W: Multiplexed I/O & Peripheral Pin P3W (General)), 2 (P3B: Multiplexed I/O & Peripheral Pin P3B (General)), 3 (CS#: Multiplexed I/O & Peripheral Pin CS# (General)), 4 (SCK: Multiplexed I/O & Peripheral Pin SCK (SPI)), 5 (SDI: Multiplexed I/O & Peripheral Pin SDI (General)), 6 (VSS: Ground Reference Pin (VSS)).

Q: What are the IPC-7351B PCB Footprint dimensions for MCP4362-103E/ST?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MCP4362-103E/ST (TSSOP-14) has a nominal body envelope of 4.40 × 5.00 mm, pitch e = 0.65 mm, and 14 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MCP4362-103E/ST?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MCP4362-103E/ST (MICROCHIP, TSSOP-14) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 4.40mm × 5.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (14/14)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	P3W	I/O	Multiplexed I/O & Peripheral Pin P3W (General)
2	P3B	I/O	Multiplexed I/O & Peripheral Pin P3B (General)
3	CS#	I/O	Multiplexed I/O & Peripheral Pin CS# (General)
4	SCK	I/O	Multiplexed I/O & Peripheral Pin SCK (SPI)
5	SDI	I/O	Multiplexed I/O & Peripheral Pin SDI (General)
6	VSS	GND	Ground Reference Pin (VSS)
7	P1B	I/O	Multiplexed I/O & Peripheral Pin P1B (General)
8	P1W	I/O	Multiplexed I/O & Peripheral Pin P1W (General)
9	P0W	I/O	Multiplexed I/O & Peripheral Pin P0W (General)
10	P0B	I/O	Multiplexed I/O & Peripheral Pin P0B (General)
11	SDO	I/O	Multiplexed I/O & Peripheral Pin SDO (General)
12	VDD	Power	Power Supply Input (VDD — 2.7V to 5.5V)
13	P2B	I/O	Multiplexed I/O & Peripheral Pin P2B (General)
14	P2W	I/O	Multiplexed I/O & Peripheral Pin P2W (General)

PIN 1 P3W

I/O

Multiplexed I/O & Peripheral Pin P3W (General)

Design note: Signal terminal P3W (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P3W. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

MCP4362-103E/ST (TSSOP-14) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

MCP4362-103E/ST (TSSOP-14) - 2. Standard Pinout (Top View)

True package pinout (14 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

MCP4362-103E/ST (TSSOP-14) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

MCP4362-103E/ST (TSSOP-14) - 4. Package Dimensions (D×E×A)

TSSOP-14 · 4.40×5.00mm · Pitch 0.65mmExpand ›

5. Recommended Land PatternLAND PATTERN

MCP4362-103E/ST (TSSOP-14) - 5. Recommended Land Pattern

IPC-7351B Footprint (14 Pads)Expand ›

6. Application SchematicSCHEMATIC

MCP4362-103E/ST (TSSOP-14) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)

Showing 1–12 of 13 uncropped original figures for MCP4362

P1 · p01_fig011777×1705px

MCP4362-103E/ST (TSSOP-14) — Features | Specified - 1.8V to 5.5V - Device Operation • Wide Bandwidth (-3 dB) Operation: - 2 MHz (typical) for 5.0 kΩ device • Extended temperature range (-40°C to +125°C) | Package Types (Top View) | MCP43X1 Quad Potentiometers | TSSOP |

Features | Specified - 1.8V to 5.5V - Device Operation • Wide Bandwidth (-3 dB) Operation: - 2 MHz (typical) for 5.0 kΩ device • Extended temperature range (-40°C to +125°C) | Package Types (Top View) | MCP43X1 Quad Potentiometers | TSSOP |

P2 · p02_fig011779×2070px

MCP4332 (3) 4 Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V

P2 · p02_fig021795×773px

P3B

P62 · p62_fig011777×695px

MCP4362-103E/ST (TSSOP-14) — FIGURE 8-4: MCP4XXX Non-volatile Digital Potentiometer Evaluation Board (MCP402XEV) implementation to generate the VIHH voltage. 8.3 Using Shutdown Modes

FIGURE 8-4: MCP4XXX Non-volatile Digital Potentiometer Evaluation Board (MCP402XEV) implementation to generate the VIHH voltage. 8.3 Using Shutdown Modes

P62 · p62_fig021576×608px

FIGURE 8-3: Using the TC1240A to Generate the VIHH Voltage.

P62 · p62_fig03867×1140px

FIGURE 8-3: Using the TC1240A to Generate the VIHH Voltage.

P63 · p63_fig011777×1273px

FIGURE 8-7: Quad Pinout (TSSOP Package) vs. Dual Pinout.

P63 · p63_fig01P63

Datasheet Page 63 (p63_fig01)

P64 · p64_fig011779×980px

Figure 8-8 shows possible layout implementations for an application to support the quad and dual options on the same PCB.

P67 · p67_fig02456×1439px

Example | 4362502E | 0940 | 256 | Example | 4361 502EML | 256 ^^3 e | Example | 0940 | MCP4361 | EST 256 | 0940 ^^3 e

P67 · p67_fig031777×754px

MCP4362-103E/ST (TSSOP-14) — © 2009 Microchip Technology Inc. DS22233A-page 67 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-spec

© 2009 Microchip Technology Inc. DS22233A-page 67 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-spec

P67 · p67_fig03P67

Datasheet Page 67 (p67_fig03)

Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (MCP4362-103E/ST)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:MCP4362-103E/ST (TSSOP-14) is a 14-pin standard electronic & interconnect component featuring a 5.00 × 4.40 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 2.7V to 5.5V supply operation across 0°C to 70°C with integrated SPI interfaces.

Operating Supply VoltageV_CC / V_DD

2.7V to 5.5V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

0°C to 70°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

10 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

5.00 × 4.40 × 1.00 mm (A1=0.10 mm)

Package family: TSSOP (TSSOP-14)

Pin Count & Lead PitchN / e

14 Pins | Pitch e = 0.65 mm (25.6 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

SPI

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol14 auto-grouped pins

IPC-7351B Land Pattern14 pads · Pitch 0.65mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TSSOP-14)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

5.00 × 4.40 mm

Height (A) & Pitch (e)IPC-7351B

A=1.00mm · e=0.65mm

Pad Size (W × L)Level B

0.42 × 1.45 mm

Pins / Total PadsTopology

14P / 14Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit TSSOP-14	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MCP4362-103E/ST (TSSOP-14)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MCP4362-103E/ST (TSSOP-14)?

Manufactured by MICROCHIP, the MCP4362-103E/ST is housed in a TSSOP-14 package with 14 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.7V to 5.5V. Key pins include: 1 (P3W: Multiplexed I/O & Peripheral Pin P3W (General)), 2 (P3B: Multiplexed I/O & Peripheral Pin P3B (General)), 3 (CS#: Multiplexed I/O & Peripheral Pin CS# (General)), 4 (SCK: Multiplexed I/O & Peripheral Pin SCK (SPI)), 5 (SDI: Multiplexed I/O & Peripheral Pin SDI (General)), 6 (VSS: Ground Reference Pin (VSS)).

What are the IPC-7351B PCB Footprint dimensions for MCP4362-103E/ST?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MCP4362-103E/ST (TSSOP-14) has a nominal body envelope of 4.40 × 5.00 mm, pitch e = 0.65 mm, and 14 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MCP4362-103E/ST?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MCP4362-103E/ST (MICROCHIP, TSSOP-14) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (14 pins) & MCP4362 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	P3W	Digital_IO	Signal terminal P3W (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P3W. Supported peripheral buses: General.
2	P3B	Digital_IO	Signal terminal P3B (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P3B. Supported peripheral buses: General.
3	CS#	Digital_IO	Signal terminal CS# (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: CS#. Supported peripheral buses: General.
4	SCK	Digital_IO	Signal terminal SCK (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SCK. Supported peripheral buses: SPI.
5	SDI	Digital_IO	Signal terminal SDI (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SDI. Supported peripheral buses: General.
6	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
7	P1B	Digital_IO	Signal terminal P1B (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P1B. Supported peripheral buses: General.
8	P1W	Digital_IO	Signal terminal P1W (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P1W. Supported peripheral buses: General.
9	P0W	Digital_IO	Signal terminal P0W (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P0W. Supported peripheral buses: General.
10	P0B	Digital_IO	Signal terminal P0B (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P0B. Supported peripheral buses: General.
11	SDO	Digital_IO	Signal terminal SDO (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SDO. Supported peripheral buses: General.
12	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.7V to 5.5V domain (Max rating: 5.5V).
13	P2B	Digital_IO	Signal terminal P2B (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P2B. Supported peripheral buses: General.
14	P2W	Digital_IO	Signal terminal P2W (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P2W. Supported peripheral buses: General.

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