Mechanical Dimensions & Land Pattern (TSSOP-16-EP)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit TSSOP-16-EP | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — DRV8833PWPR (TSSOP-16-EP)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of DRV8833PWPR (TSSOP-16-EP)?
Manufactured by TI, the DRV8833PWPR is housed in a TSSOP-16-EP package with 17 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.7 V to 10.8 V. Key pins include: 1 (nSLEEP: Multiplexed I/O & Peripheral Pin nSLEEP (General)), 2 (AOUT1: Multiplexed I/O & Peripheral Pin AOUT1 (General)), 3 (AISEN: Multiplexed I/O & Peripheral Pin AISEN (General)), 4 (AOUT2: Multiplexed I/O & Peripheral Pin AOUT2 (General)), 5 (BOUT2: Multiplexed I/O & Peripheral Pin BOUT2 (General)), 6 (BISEN: Multiplexed I/O & Peripheral Pin BISEN (General)).
What are the IPC-7351B PCB Footprint dimensions for DRV8833PWPR?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), DRV8833PWPR (TSSOP-16-EP) has a nominal body envelope of 4.40 × 5.00 mm, pitch e = 0.65 mm, and 17 copper pads plus a central exposed thermal pad (EPAD) of 2.73 × 3.20 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for DRV8833PWPR?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for DRV8833PWPR (TI, TSSOP-16-EP) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (17 pins) & DRV8833 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | nSLEEP | Digital_IO | Signal terminal nSLEEP (I/O, 2.7 V to 10.8 V domain). Multiplexed alternate functions: nSLEEP. Supported peripheral buses: General. |
| 2 | AOUT1 | Digital_IO | Signal terminal AOUT1 (I/O, 2.7 V to 10.8 V domain). Multiplexed alternate functions: AOUT1. Supported peripheral buses: General. |
| 3 | AISEN | Digital_IO | Signal terminal AISEN (I/O, 2.7 V to 10.8 V domain). Multiplexed alternate functions: AISEN. Supported peripheral buses: General. |
| 4 | AOUT2 | Digital_IO | Signal terminal AOUT2 (I/O, 2.7 V to 10.8 V domain). Multiplexed alternate functions: AOUT2. Supported peripheral buses: General. |
| 5 | BOUT2 | Digital_IO | Signal terminal BOUT2 (I/O, 2.7 V to 10.8 V domain). Multiplexed alternate functions: BOUT2. Supported peripheral buses: General. |
| 6 | BISEN | Digital_IO | Signal terminal BISEN (I/O, 2.7 V to 10.8 V domain). Multiplexed alternate functions: BISEN. Supported peripheral buses: General. |
| 7 | BOUT1 | Digital_IO | Signal terminal BOUT1 (I/O, 2.7 V to 10.8 V domain). Multiplexed alternate functions: BOUT1. Supported peripheral buses: General. |
| 8 | nFault | Digital_IO | Signal terminal nFault (I/O, 2.7 V to 10.8 V domain). Multiplexed alternate functions: nFault. Supported peripheral buses: General. |
| 9 | BIN1 | Digital_IO | Signal terminal BIN1 (I/O, 2.7 V to 10.8 V domain). Multiplexed alternate functions: BIN1. Supported peripheral buses: General. |
| 10 | BIN2 | Digital_IO | Signal terminal BIN2 (I/O, 2.7 V to 10.8 V domain). Multiplexed alternate functions: BIN2. Supported peripheral buses: General. |
| 11 | VCP | Digital_IO | Signal terminal VCP (I/O, 2.7 V to 10.8 V domain). Multiplexed alternate functions: VCP. Supported peripheral buses: General. |
| 12 | VM | Digital_IO | Signal terminal VM (I/O, 2.7 V to 10.8 V domain). Multiplexed alternate functions: VM. Supported peripheral buses: General. |
| 13 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 14 | VINT | Power_In | Primary positive power supply input (VINT) operating in the 2.7 V to 10.8 V domain (Max rating: 10.8V). |
| 15 | AIN2 | Analog | Signal terminal AIN2 (I/O, 2.7 V to 10.8 V domain). Multiplexed alternate functions: AIN2. Supported peripheral buses: ADC. |
| 16 | AIN1 | Analog | Signal terminal AIN1 (I/O, 2.7 V to 10.8 V domain). Multiplexed alternate functions: AIN1. Supported peripheral buses: ADC. |
| 17 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |