ChipDocs.org
⌘K
2284 PARTSUpload PDF
PIC16F631-I/SO (SOIC-20-300mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC16F631-I/SO

MICROCHIPID: C47279SOIC-20-300mil · 20 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC16F631-I/SO (SOIC-20-300mil)1VDD2RA5/T1CKI/OS3RA4/T1G#/OSC4RA3/MCLR#/VP5RC56RC4/C2OUT7RC3/C12IN3-8RC69RC710RB720VSS19IO2018RA1C12IN0-IC17RA2/T0CKI/IN16RC0/C2IN+15RC1/C12IN1-14RC2/C12IN2-13RB412RB511RB6Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=7.50mm · Pitch e=1.27mmD=12.80mm-9-7-5-3-11357997531-1-3-5-7-9mm
3. 3D CAD MODEL
Package Body: 7.50mm × 12.80mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDDPowerPower Supply Input (VDD — 2.0V-5.5V)
2RA5/T1CKI/OSC1/CLKINI/OMultiplexed I/O & Peripheral Pin RA5/T1CKI/OSC1/CLKIN (RTC/CLK)
3RA4/T1G#/OSC2/CLKOUTI/OMultiplexed I/O & Peripheral Pin RA4/T1G#/OSC2/CLKOUT (RTC/CLK)
4RA3/MCLR#/VPPI/OMultiplexed I/O & Peripheral Pin RA3/MCLR#/VPP (General)
5RC5I/OMultiplexed I/O & Peripheral Pin RC5 (General)
6RC4/C2OUTI/OMultiplexed I/O & Peripheral Pin RC4/C2OUT (General)
7RC3/C12IN3-I/OMultiplexed I/O & Peripheral Pin RC3/C12IN3- (General)
8RC6I/OMultiplexed I/O & Peripheral Pin RC6 (General)
9RC7I/OMultiplexed I/O & Peripheral Pin RC7 (General)
10RB7I/OMultiplexed I/O & Peripheral Pin RB7 (General)
11RB6I/OMultiplexed I/O & Peripheral Pin RB6 (General)
12RB5I/OMultiplexed I/O & Peripheral Pin RB5 (General)
13RB4I/OMultiplexed I/O & Peripheral Pin RB4 (General)
14RC2/C12IN2-I/OMultiplexed I/O & Peripheral Pin RC2/C12IN2- (General)
15RC1/C12IN1-I/OMultiplexed I/O & Peripheral Pin RC1/C12IN1- (General)
16RC0/C2IN+I/OMultiplexed I/O & Peripheral Pin RC0/C2IN+ (General)
17RA2/T0CKI/INT/C1OUTI/OMultiplexed I/O & Peripheral Pin RA2/T0CKI/INT/C1OUT (General)
18RA1C12IN0-ICSPCLKI/OMultiplexed I/O & Peripheral Pin RA1C12IN0-ICSPCLK (General)
19IO20I/OGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20VSSGNDGround Reference Pin (VSS)
PIN 1 VDD
Power
Power Supply Input (VDD — 2.0V-5.5V)
Design note: VDD
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC16F631-I/SO (MICROCHIP · SOIC-20-300mil)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC16F631-I/SO (SOIC-20-300mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC16F631-I/SO (SOIC-20-300mil) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC16F631-I/SO (SOIC-20-300mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC16F631-I/SO (SOIC-20-300mil) - 4. Package Dimensions (D×E×A)
SOIC-20-300mil · 7.50×12.80mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC16F631-I/SO (SOIC-20-300mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC16F631-I/SO (SOIC-20-300mil) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for PIC16F631 / PIC16F689
P2 · p02_fig011777×1639px
PIC16F631-I/SO (SOIC-20-300mil) — DS41262E-page ii © 2008 Microchip Technology Inc. | Trademarks | FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporate
DS41262E-page ii © 2008 Microchip Technology Inc. | Trademarks | FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporate
P2 · p02_fig02782×281px
PIC16F631-I/SO (SOIC-20-300mil) — DS41262E-page ii © 2008 Microchip Technology Inc.
DS41262E-page ii © 2008 Microchip Technology Inc.
P130 · p130_fig011753×625px
PIC16F631-I/SO (SOIC-20-300mil) — FIGURE 11-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
FIGURE 11-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
P131 · p131_fig01867×847px
PIC16F631-I/SO (SOIC-20-300mil) — FIGURE 11-2: COMPARE MODE OPERATION BLOCK DIAGRAM
FIGURE 11-2: COMPARE MODE OPERATION BLOCK DIAGRAM
P135 · p135_fig011558×987px
PIC16F631-I/SO (SOIC-20-300mil) — FIGURE 11-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE Duty Cycle Registers
FIGURE 11-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE Duty Cycle Registers
P185 · p185_fig011777×937px
PIC16F631-I/SO (SOIC-20-300mil) — FIGURE 13-2: SPI MASTER/SLAVE CONNECTION
FIGURE 13-2: SPI MASTER/SLAVE CONNECTION
P192 · p192_fig011731×641px
PIC16F631-I/SO (SOIC-20-300mil) — FIGURE 13-8: I2C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
FIGURE 13-8: I2C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
P192 · p192_fig01P192
PIC16F631-I/SO (SOIC-20-300mil) — Datasheet Page 192 (p192_fig01)
Datasheet Page 192 (p192_fig01)
P194 · p194_fig011777×2496px
PIC16F631-I/SO (SOIC-20-300mil) — FIGURE 13-9: I2C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)
FIGURE 13-9: I2C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)
P289 · p289_fig01All Packages in PDF
PIC16F631-I/SO (SOIC-20-300mil) — PIC16F631/677/685/687/689/690
PIC16F631/677/685/687/689/690

Technical Specifications & Part Details (PIC16F631-I/SO)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC16F631-I/SO (SOIC-20-300mil) is a 20-pin standard electronic & interconnect component featuring a 12.80 × 7.50 × 2.70 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 2.0V-5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
2.0V-5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
12.80 × 7.50 × 2.70 mm (A1=0.20 mm)
Package family: SOIC (SOIC-20-300mil)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — PIC16F631 / PIC16F689 (2)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (SOIC-20-300mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
12.80 × 7.50 mm
Height (A) & Pitch (e)IPC-7351B
A=2.70mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.90 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOIC-20-300mil
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC16F631-I/SO (SOIC-20-300mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC16F631-I/SO (SOIC-20-300mil)?

Manufactured by MICROCHIP, the PIC16F631-I/SO is housed in a SOIC-20-300mil package with 20 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 2.0V-5.5V. Key pins include: 1 (VDD: Power Supply Input (VDD — 2.0V-5.5V)), 2 (RA5/T1CKI/OSC1/CLKIN: Multiplexed I/O & Peripheral Pin RA5/T1CKI/OSC1/CLKIN (RTC/CLK)), 3 (RA4/T1G#/OSC2/CLKOUT: Multiplexed I/O & Peripheral Pin RA4/T1G#/OSC2/CLKOUT (RTC/CLK)), 4 (RA3/MCLR#/VPP: Multiplexed I/O & Peripheral Pin RA3/MCLR#/VPP (General)), 5 (RC5: Multiplexed I/O & Peripheral Pin RC5 (General)), 6 (RC4/C2OUT: Multiplexed I/O & Peripheral Pin RC4/C2OUT (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC16F631-I/SO?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16F631-I/SO (SOIC-20-300mil) has a nominal body envelope of 7.50 × 12.80 mm, pitch e = 1.27 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16F631-I/SO?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16F631-I/SO (MICROCHIP, SOIC-20-300mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & PIC16F631 / PIC16F689 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDDPower_InPrimary positive power supply input (VDD) operating in the 2.0V-5.5V domain (Max rating: 5.5V).
2RA5/T1CKI/OSC1/CLKINDigital_IOSignal terminal RA5/T1CKI/OSC1/CLKIN (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RA5/T1CKI/OSC1/CLKIN. Supported peripheral buses: RTC/CLK.
3RA4/T1G#/OSC2/CLKOUTDigital_IOSignal terminal RA4/T1G#/OSC2/CLKOUT (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RA4/T1G#/OSC2/CLKOUT. Supported peripheral buses: RTC/CLK.
4RA3/MCLR#/VPPDigital_IOSignal terminal RA3/MCLR#/VPP (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RA3/MCLR#/VPP. Supported peripheral buses: General.
5RC5Digital_IOSignal terminal RC5 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RC5. Supported peripheral buses: General.
6RC4/C2OUTDigital_IOSignal terminal RC4/C2OUT (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RC4/C2OUT. Supported peripheral buses: General.
7RC3/C12IN3-Digital_IOSignal terminal RC3/C12IN3- (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RC3/C12IN3-. Supported peripheral buses: General.
8RC6Digital_IOSignal terminal RC6 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RC6. Supported peripheral buses: General.
9RC7Digital_IOSignal terminal RC7 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RC7. Supported peripheral buses: General.
10RB7Digital_IOSignal terminal RB7 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RB7. Supported peripheral buses: General.
11RB6Digital_IOSignal terminal RB6 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RB6. Supported peripheral buses: General.
12RB5Digital_IOSignal terminal RB5 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RB5. Supported peripheral buses: General.
13RB4Digital_IOSignal terminal RB4 (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RB4. Supported peripheral buses: General.
14RC2/C12IN2-Digital_IOSignal terminal RC2/C12IN2- (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RC2/C12IN2-. Supported peripheral buses: General.
15RC1/C12IN1-Digital_IOSignal terminal RC1/C12IN1- (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RC1/C12IN1-. Supported peripheral buses: General.
16RC0/C2IN+Digital_IOSignal terminal RC0/C2IN+ (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RC0/C2IN+. Supported peripheral buses: General.
17RA2/T0CKI/INT/C1OUTDigital_IOSignal terminal RA2/T0CKI/INT/C1OUT (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RA2/T0CKI/INT/C1OUT. Supported peripheral buses: General.
18RA1C12IN0-ICSPCLKDigital_IOSignal terminal RA1C12IN0-ICSPCLK (I/O, 2.0V-5.5V domain). Multiplexed alternate functions: RA1C12IN0-ICSPCLK. Supported peripheral buses: General.
19IO20Digital_IOGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
ExplorePartsPackagesMFRsUpload