Mechanical Dimensions & Land Pattern (DIP-8)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| C_ctrl BOM | 10nF (0.01µF) Ceramic 0603 / Disc | Keep traces as short as possible, place decoupling caps close to VCC pin. |
| C_dec BOM | 100nF Ceramic + 10µF Electrolytic Radial / 0805 | Supply transient bypass (~150mA shoot-through spikes) on VCC (Pin 8) — place adjacent to Pins 8-1. |
| R1, R2 + C_timing BOM | R1=4.7kΩ, R2=47kΩ, C=100nF 0603 / THT | RC timing network on DISCH (Pin 7), THRES (Pin 6), TRIG (Pin 2) — tie RESET (Pin 4) to VCC if unused. |
| SA555P / SE555P Texas Instruments | 100% Drop-in | 100% Pin-to-Pin DIP-8 equivalent for 555 timer designs. |
| TLC555CP / LMC555CN Texas Instruments | 100% Drop-in | 100% Pin-to-Pin DIP-8 equivalent for 555 timer designs. |
Technical Frequently Asked Questions (FAQ) — NE555P (DIP-8)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of NE555P (DIP-8)?
Manufactured by TI, the NE555P is housed in a DIP-8 package with 8 pins and a 2.54 mm lead pitch, supporting a VCC supply range of 4.5 V to 16 V. Key pins include: 1 (GND: Ground Reference Pin (GND)), 2 (TRIG: NE555 Precision Timer Terminal (TRIG)), 3 (OUT: NE555 Precision Timer Terminal (OUT)), 4 (RESET: System Enable & Hardware Reset (RESET)), 5 (CONT: NE555 Precision Timer Terminal (CONT)), 6 (THRES: NE555 Precision Timer Terminal (THRES)).
What are the IPC-7351B PCB Footprint dimensions for NE555P?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), NE555P (DIP-8) has a nominal body envelope of 6.35 × 9.62 mm, pitch e = 2.54 mm, and 8 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for NE555P?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for NE555P (TI, DIP-8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (8 pins) & NE555 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 2 | TRIG | Analog | Trigger comparator input (< 1/3 VCC sets flip-flop and drives OUT high) |
| 3 | OUT | Digital_IO | Push-pull timer output stage (capable of sinking or sourcing up to 200mA) |
| 4 | RESET | Digital_IO | Active-low hardware reset terminal (RESET): pulling this pin Low resets the processor core and peripherals. |
| 5 | CONT | Analog | Internal 2/3 VCC voltage divider access (bypass to GND via 10nF capacitor) |
| 6 | THRES | Analog | Threshold comparator input (> 2/3 VCC resets flip-flop and drives OUT low) |
| 7 | DISCH | Open_Drain | Open-collector discharge transistor terminal for timing capacitor |
| 8 | VCC | Power_In | Primary positive power supply input (VCC) operating in the 4.5V ~ 16.0V VCC domain (Max rating: 18.0V). |