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STM32WB55RGV6 (QFN-68-EP(8x8)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32WB55RGV6

STID: C401505QFN-68-EP(8x8) · 69 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32WB55RGV6 (QFN-68-EP(8x8))1VBAT2PC133PC14-OSC32_I4PC15-OSC32_O5PH3-BOOT06PB87PB98NRST9PC010PC111PC212PC313VREF+14VDDA15PA016PA117PA218PA319PA420PA521PA622PA723PA824PA925PC426PC527PB228PB1029PB1130VDD31RF132VSSRF33VDDRF34OSC_OUT35OSC_IN69EP68VDD67PB766PB665PB564PB4 (NJTRST)63PB3 (JTDO)62PD161PD060PC1259PC1158PC1057PA15 (JTDI)56PA14 (JTCK_S55VDDUSB54PA13 (JTMS S53PA1252PA1151PA1050PC649PB1548PB1447PB1346PB1245VDD44VDDSMPS43VLXSMPS42VSSSMPS41VFBSMPS40PE439PB138PB037AT136AT0Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.850.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869E=8.00mm · Pitch e=0.40mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (69/69)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
2PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
3PC14-OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
4PC15-OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)
5PH3-BOOT0I/OMultiplexed I/O & Peripheral Pin PH3-BOOT0 (General)
6PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
7PB9I/OMultiplexed I/O & Peripheral Pin PB9 (I2C)
8NRSTISystem Enable & Hardware Reset (NRST)
9PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
10PC1I/OMultiplexed I/O & Peripheral Pin PC1 (I2C, ADC)
11PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
12PC3I/OMultiplexed I/O & Peripheral Pin PC3 (ADC)
13VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
14VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
15PA0I/OMultiplexed I/O & Peripheral Pin PA0 (PWM, RTC/CLK)
16PA1I/OMultiplexed I/O & Peripheral Pin PA1 (SPI, PWM)
17PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
18PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
19PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI)
20PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, PWM)
21PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, ADC)
22PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
23PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, SPI, ADC, RTC/CLK)
24PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, I2C)
25PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
26PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
27PB2I/OMultiplexed I/O & Peripheral Pin PB2 (I2C, RTC/CLK)
28PB10I/OMultiplexed I/O & Peripheral Pin PB10 (SPI, PWM)
29PB11I/OMultiplexed I/O & Peripheral Pin PB11 (PWM)
30VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
31RF1I/OMultiplexed I/O & Peripheral Pin RF1 (General)
32VSSRFGNDGround Reference Pin (VSSRF)
33VDDRFPowerPower Supply Input (VDDRF — 3.3V VDD (Max 4.0V))
34OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
35OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
36AT0I/OMultiplexed I/O & Peripheral Pin AT0 (General)
37AT1I/OMultiplexed I/O & Peripheral Pin AT1 (General)
38PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
39PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART)
40PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
41VFBSMPSI/OMultiplexed I/O & Peripheral Pin VFBSMPS (General)
42VSSSMPSGNDGround Reference Pin (VSSSMPS)
43VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
44VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
45VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
46PB12I/OMultiplexed I/O & Peripheral Pin PB12 (SPI)
47PB13I/OMultiplexed I/O & Peripheral Pin PB13 (SPI, PWM)
48PB14I/OMultiplexed I/O & Peripheral Pin PB14 (SPI, PWM)
49PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, RTC/CLK)
50PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
51PA10I/OMultiplexed I/O & Peripheral Pin PA10 (USB, I2C)
52PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, SPI, PWM)
53PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART)
54PA13 (JTMS SWDIO)_I/OMultiplexed I/O & Peripheral Pin PA13 (JTMS SWDIO)_ (USB, SWD/JTAG)
55VDDUSBPowerPower Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))
56PA14 (JTCK_SWCLK )I/OMultiplexed I/O & Peripheral Pin PA14 (JTCK_SWCLK ) (I2C, SWD/JTAG)
57PA15 (JTDI)I/OMultiplexed I/O & Peripheral Pin PA15 (JTDI) (SPI, SWD/JTAG)
58PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
59PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
60PC12I/OMultiplexed I/O & Peripheral Pin PC12 (RTC/CLK)
61PD0I/OMultiplexed I/O & Peripheral Pin PD0 (SPI)
62PD1I/OMultiplexed I/O & Peripheral Pin PD1 (SPI)
63PB3 (JTDO)I/OMultiplexed I/O & Peripheral Pin PB3 (JTDO) (UART, PWM, SWD/JTAG)
64PB4 (NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4 (NJTRST) (SPI, I2C, SWD/JTAG)
65PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI)
66PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART)
67PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C)
68VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
69EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 VBAT
Power
Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 33 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32WB55RGV6 (ST · QFN-68-EP(8x8))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32WB55RGV6 (QFN-68-EP(8x8)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32WB55RGV6 (QFN-68-EP(8x8)) - 2. Standard Pinout (Top View)
True package pinout (69 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32WB55RGV6 (QFN-68-EP(8x8)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32WB55RGV6 (QFN-68-EP(8x8)) - 4. Package Dimensions (D×E×A)
QFN-68-EP(8x8) · 8.00×8.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32WB55RGV6 (QFN-68-EP(8x8)) - 5. Recommended Land Pattern
IPC-7351B Footprint (69 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32WB55RGV6 (QFN-68-EP(8x8)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (33 figures · Page 1/3)
Showing 1–12 of 33 uncropped original figures for STM32WB55 / STM32WB35
P25 · p25_fig011752×1223px
STM32WB55RGV6 (QFN-68-EP(8x8)) — Figure 4. Power distribution
Figure 4. Power distribution
P54 · p54_fig021546×1136px
STM32WB55RGV6 (QFN-68-EP(8x8)) — Figure 9. STM32WB55Rx VFQFPN68 pinout(1)(2)
Figure 9. STM32WB55Rx VFQFPN68 pinout(1)(2)
P54 · p54_fig02P54
STM32WB55RGV6 (QFN-68-EP(8x8)) — Datasheet Page 54 (p54_fig02)
Datasheet Page 54 (p54_fig02)
P109 · p109_fig011875×957px
STM32WB55RGV6 (QFN-68-EP(8x8)) — Figure 19. Typical application with a 32.768 kHz crystal
Figure 19. Typical application with a 32.768 kHz crystal
P109 · p109_fig01P109
STM32WB55RGV6 (QFN-68-EP(8x8)) — Datasheet Page 109 (p109_fig01)
Datasheet Page 109 (p109_fig01)
P140 · p140_fig011546×641px
STM32WB55RGV6 (QFN-68-EP(8x8)) — Figure 26. Typical connection diagram using the ADC
Figure 26. Typical connection diagram using the ADC
P157 · p157_fig011550×1059px
STM32WB55RGV6 (QFN-68-EP(8x8)) — Figure 34. UFBGA - 129 balls, 7 x 7 mm, 0.5 mm fine pitch, square ball grid array
Figure 34. UFBGA - 129 balls, 7 x 7 mm, 0.5 mm fine pitch, square ball grid array
P157 · p157_fig021875×755px
STM32WB55RGV6 (QFN-68-EP(8x8)) — DS11929 Rev 4 157/172 | 166 | Table 94. UFBGA - 129 balls, 7 x 7 mm, 0.5 mm fine pitch, square ball grid array | mechanical data | Symbol | millimeters inches(1) | Min Typ Max Min Typ Max | A(2) - - 0.60 - - 0.024 | A1 - - 0.11 - - 0.004 |
DS11929 Rev 4 157/172 | 166 | Table 94. UFBGA - 129 balls, 7 x 7 mm, 0.5 mm fine pitch, square ball grid array | mechanical data | Symbol | millimeters inches(1) | Min Typ Max Min Typ Max | A(2) - - 0.60 - - 0.024 | A1 - - 0.11 - - 0.004 |
P158 · p158_fig011546×722px
STM32WB55RGV6 (QFN-68-EP(8x8)) — Figure 35. UFBGA - 129 balls, 7 x 7 mm, 0.5 mm fine pitch, square ball grid array
Figure 35. UFBGA - 129 balls, 7 x 7 mm, 0.5 mm fine pitch, square ball grid array
P159 · p159_fig011752×657px
STM32WB55RGV6 (QFN-68-EP(8x8)) — Figure 36. VFQFPN68, 8 x 8 mm, 0.4 mm pitch, very thin fine pitch quad flat
Figure 36. VFQFPN68, 8 x 8 mm, 0.4 mm pitch, very thin fine pitch quad flat
P159 · p159_fig021546×1316px
STM32WB55RGV6 (QFN-68-EP(8x8)) — Figure 36. VFQFPN68, 8 x 8 mm, 0.4 mm pitch, very thin fine pitch quad flat
Figure 36. VFQFPN68, 8 x 8 mm, 0.4 mm pitch, very thin fine pitch quad flat
P159 · p159_fig02P159
STM32WB55RGV6 (QFN-68-EP(8x8)) — Datasheet Page 159 (p159_fig02)
Datasheet Page 159 (p159_fig02)
Page 1 / 3 (33 extracted figures)

Technical Specifications & Part Details (STM32WB55RGV6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32WB55RGV6 (QFN-68-EP(8x8)) is a 68-pin embedded microcontroller unit (mcu) featuring a 8.00 × 8.00 × 0.90 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, UART, SPI, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
42 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 0.90 mm (A1=0.04 mm)
Package family: QFN (QFN-68-EP(8x8))
Pin Count & Lead PitchN / e
68 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, UART, SPI, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3-BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol69 auto-grouped pins
OK
IPC-7351B Land Pattern69 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 6.40×6.40mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — STM32WB55 / STM32WB35 (20)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (QFN-68-EP(8x8))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.40mm
Pad Size (W × L)Level B
0.24 × 0.90 mm
Pins / Total PadsTopology
69P / 69Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-68-EP(8x8)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32WB55RGV6 (QFN-68-EP(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32WB55RGV6 (QFN-68-EP(8x8))?

Manufactured by ST, the STM32WB55RGV6 is housed in a QFN-68-EP(8x8) package with 69 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (General)), 3 (PC14-OSC32_IN: Multiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)), 4 (PC15-OSC32_OUT: Multiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)), 5 (PH3-BOOT0: Multiplexed I/O & Peripheral Pin PH3-BOOT0 (General)), 6 (PB8: Multiplexed I/O & Peripheral Pin PB8 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32WB55RGV6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32WB55RGV6 (QFN-68-EP(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.40 mm, and 69 copper pads plus a central exposed thermal pad (EPAD) of 6.40 × 6.40 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32WB55RGV6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32WB55RGV6 (ST, QFN-68-EP(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (69 pins) & STM32WB55 / STM32WB35 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
2PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
3PC14-OSC32_INDigital_IOSignal terminal PC14-OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK.
4PC15-OSC32_OUTDigital_IOSignal terminal PC15-OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK.
5PH3-BOOT0Digital_IOSignal terminal PH3-BOOT0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH3-BOOT0. Supported peripheral buses: General.
6PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
7PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: I2C.
8NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
9PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
10PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: I2C, ADC.
11PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: ADC.
12PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: ADC.
13VREF+AnalogSignal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
14VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
15PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: PWM, RTC/CLK.
16PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCKLCDSEG0. Supported peripheral buses: SPI, PWM.
17PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
18PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
19PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS_SAI1FSB. Supported peripheral buses: SPI.
20PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCKLPTIM2ETR. Supported peripheral buses: SPI, PWM.
21PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: UART, ADC.
22PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
23PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, SPI, ADC, RTC/CLK.
24PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, I2C.
25PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General.
26PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General.
27PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: I2C, RTC/CLK.
28PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKLPUART1RX. Supported peripheral buses: SPI, PWM.
29PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: PWM.
30VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
31RF1RF_50OhmSignal terminal RF1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: RF1. Supported peripheral buses: General.
32VSSRFGND0V electrical ground return terminal (VSSRF) for internal core logic, I/O drivers, and analog sub-blocks.
33VDDRFPower_InPrimary positive power supply input (VDDRF) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
34OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
35OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
36AT0Digital_IOSignal terminal AT0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: AT0. Supported peripheral buses: General.
37AT1Digital_IOSignal terminal AT1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: AT1. Supported peripheral buses: General.
38PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
39PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART.
40PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
41VFBSMPSDigital_IOSignal terminal VFBSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VFBSMPS. Supported peripheral buses: General.
42VSSSMPSGND0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
43VLXSMPSDigital_IOSignal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General.
44VDDSMPSPower_InPrimary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
45VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
46PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSSLPUART1RTS. Supported peripheral buses: SPI.
47PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKLPUART1CTS. Supported peripheral buses: SPI, PWM.
48PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO_TSCG1IO3. Supported peripheral buses: SPI, PWM.
49PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI_TSCG1IO4. Supported peripheral buses: SPI, RTC/CLK.
50PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
51PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: USB, I2C.
52PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOUSART1CTS. Supported peripheral buses: USB, SPI, PWM.
53PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART.
54PA13 (JTMS SWDIO)_Digital_IOSignal terminal PA13 (JTMS SWDIO)_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (JTMS SWDIO)_. Supported peripheral buses: USB, SWD/JTAG.
55VDDUSBPower_InPrimary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
56PA14 (JTCK_SWCLK )Digital_IOSignal terminal PA14 (JTCK_SWCLK ) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14 (JTCK_SWCLK ). Supported peripheral buses: I2C, SWD/JTAG.
57PA15 (JTDI)Digital_IOSignal terminal PA15 (JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS_TSCG3IO1. Supported peripheral buses: SPI, SWD/JTAG.
58PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
59PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
60PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: RTC/CLK.
61PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSSCM4EVENTOUT. Supported peripheral buses: SPI.
62PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKCM4EVENTOUT. Supported peripheral buses: SPI.
63PB3 (JTDO)Digital_IOSignal terminal PB3 (JTDO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB3 (JTDO). Supported peripheral buses: UART, PWM, SWD/JTAG.
64PB4 (NJTRST)Digital_IOSignal terminal PB4 (NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA, SPI1_MISOUSART1CTS. Supported peripheral buses: SPI, I2C, SWD/JTAG.
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