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STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32WB55VCY7TR

STID: C1857723WLCSP-100(4.4x4.4) · 100 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32WB55VCY7TR (WLCSP-100(4.4x4.4))A1PA11A2PA12A3PA14 (JTCK SA4PA15 (JTDI)A5PA13 (JTMS SA6PC10A7PD2A8PD7A9PB3 (JTDO)A10VDDB1VDDB2VSSB3VDDUSBB4PC9B5PA10B6PC11B7PD5B8PD12B9VSSB10PE1C1PB13C2PD3C3PD1C4PD0C5PC12C6PD6C7PB4 (NJTRST)C8PE0C9PD13C10VBATD1VDDSMPSD2PC6D3PD4D4PD8D5PD9D6PB5D7PB7D8PD14D9PC15 - OSC32D10PC14 - OSC32E1VLXSMPSE2PB14E3PC7E4PD10E5PD11E6PE2E7PD15E8PH3 BOOT0 -E9PH1E10PH0K10PA4K9PA5K8PA9K7PB2K6PB10K5VDDK4RF1K3VSSRFK2VSSRFK1VSSRFJ10VDDJ9VSSJ8PA3J7PA8J6PB11J5VSSJ4VSSRFJ3VDDRFJ2OSC_OUTJ1OSC_INH10VSSAH9VDDAH8VREF+H7PA6H6PA7H5PC5H4AT1H3AT0H2PB0H1PB1G10PC3G9PC2G8PC1G7PA0G6PA1G5PC13G4PC4G3PB12G2PE3G1PE4F10PB9F9NRSTF8PC0F7PB8F6PA2F5PB6F4PC8F3PB15F2VFBSMPSF1VSSSMPSGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1K1A2B2C2D2E2F2G2H2J2K2A3B3C3D3E3F3G3H3J3K3A4B4C4D4E4F4G4H4J4K4A5B5C5D5E5F5G5H5J5K5A6B6C6D6E6F6G6H6J6K6A7B7C7D7E7F7G7H7J7K7A8B8C8D8E8F8G8H8J8K8A9B9C9D9E9F9G9H9J9K9A10B10C10D10E10F10G10H10J10K10E=4.40mm · Pitch e=0.40mmD=4.40mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.40mm × 4.40mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, SPI, PWM)
A2PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART)
A3PA14 (JTCK SWCLK)_I/OMultiplexed I/O & Peripheral Pin PA14 (JTCK SWCLK)_ (I2C, SWD/JTAG)
A4PA15 (JTDI)I/OMultiplexed I/O & Peripheral Pin PA15 (JTDI) (SPI, SWD/JTAG)
A5PA13 (JTMS SWDIO)_I/OMultiplexed I/O & Peripheral Pin PA13 (JTMS SWDIO)_ (USB, SWD/JTAG)
A6PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
A7PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
A8PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
A9PB3 (JTDO)I/OMultiplexed I/O & Peripheral Pin PB3 (JTDO) (UART, PWM, SWD/JTAG)
A10VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
B1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
B2VSSGNDGround Reference Pin (VSS)
B3VDDUSBPowerPower Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))
B4PC9I/OMultiplexed I/O & Peripheral Pin PC9 (USB, SPI)
B5PA10I/OMultiplexed I/O & Peripheral Pin PA10 (USB, I2C)
B6PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
B7PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
B8PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
B9VSSGNDGround Reference Pin (VSS)
B10PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
C1PB13I/OMultiplexed I/O & Peripheral Pin PB13 (SPI, PWM)
C2PD3I/OMultiplexed I/O & Peripheral Pin PD3 (SPI)
C3PD1I/OMultiplexed I/O & Peripheral Pin PD1 (SPI)
C4PD0I/OMultiplexed I/O & Peripheral Pin PD0 (SPI)
C5PC12I/OMultiplexed I/O & Peripheral Pin PC12 (RTC/CLK)
C6PD6I/OMultiplexed I/O & Peripheral Pin PD6 (I2C)
C7PB4 (NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4 (NJTRST) (SPI, I2C, SWD/JTAG)
C8PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
C9PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
C10VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
D1VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
D2PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
D3PD4I/OMultiplexed I/O & Peripheral Pin PD4 (SPI)
D4PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
D5PD9I/OMultiplexed I/O & Peripheral Pin PD9 (General)
D6PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI)
D7PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C)
D8PD14I/OMultiplexed I/O & Peripheral Pin PD14 (PWM)
D9PC15 - OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK)
D10PC14 - OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (RTC/CLK)
E1VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
E2PB14I/OMultiplexed I/O & Peripheral Pin PB14 (SPI, PWM)
E3PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
E4PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
E5PD11I/OMultiplexed I/O & Peripheral Pin PD11 (General)
E6PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
E7PD15I/OMultiplexed I/O & Peripheral Pin PD15 (PWM)
E8PH3 BOOT0 -I/OMultiplexed I/O & Peripheral Pin PH3 BOOT0 - (General)
E9PH1I/OMultiplexed I/O & Peripheral Pin PH1 (General)
E10PH0I/OMultiplexed I/O & Peripheral Pin PH0 (General)
F1VSSSMPSGNDGround Reference Pin (VSSSMPS)
F2VFBSMPSI/OMultiplexed I/O & Peripheral Pin VFBSMPS (General)
F3PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, RTC/CLK)
F4PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
F5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART)
F6PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
F7PB8I/OMultiplexed I/O & Peripheral Pin PB8 (PWM)
F8PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
F9NRSTISystem Enable & Hardware Reset (NRST)
F10PB9I/OMultiplexed I/O & Peripheral Pin PB9 (I2C)
G1PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
G2PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
G3PB12I/OMultiplexed I/O & Peripheral Pin PB12 (SPI)
G4PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
G5PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
G6PA1I/OMultiplexed I/O & Peripheral Pin PA1 (SPI, PWM)
G7PA0I/OMultiplexed I/O & Peripheral Pin PA0 (PWM, RTC/CLK)
G8PC1I/OMultiplexed I/O & Peripheral Pin PC1 (I2C, ADC)
G9PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
G10PC3I/OMultiplexed I/O & Peripheral Pin PC3 (ADC)
H1PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART)
H2PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
H3AT0I/OMultiplexed I/O & Peripheral Pin AT0 (General)
H4AT1I/OMultiplexed I/O & Peripheral Pin AT1 (General)
H5PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
H6PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
H7PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, ADC)
H8VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
H9VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
H10VSSAGNDGround Reference Pin (VSSA)
J1OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
J2OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
J3VDDRFPowerPower Supply Input (VDDRF — 3.3V VDD (Max 4.0V))
J4VSSRFGNDGround Reference Pin (VSSRF)
J5VSSGNDGround Reference Pin (VSS)
J6PB11I/OMultiplexed I/O & Peripheral Pin PB11 (PWM)
J7PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, SPI, ADC, RTC/CLK)
J8PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
J9VSSGNDGround Reference Pin (VSS)
J10VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
K1VSSRFGNDGround Reference Pin (VSSRF)
K2VSSRFGNDGround Reference Pin (VSSRF)
K3VSSRFGNDGround Reference Pin (VSSRF)
K4RF1I/OMultiplexed I/O & Peripheral Pin RF1 (General)
K5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
K6PB10I/OMultiplexed I/O & Peripheral Pin PB10 (SPI, PWM)
K7PB2I/OMultiplexed I/O & Peripheral Pin PB2 (I2C, RTC/CLK)
K8PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, I2C)
K9PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, PWM)
K10PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI)
PIN A1 PA11
I/O
Multiplexed I/O & Peripheral Pin PA11 (USB, SPI, PWM)
Design note: Alt: TIM1_CH4TIM1BKIN2 ,_ , SPI1_MISOUSART1CTS ,_ , USB_DMCM4EVENTOUT ,_
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32WB55VCY7TR (ST · WLCSP-100(4.4x4.4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) - 4. Package Dimensions (D×E×A)
WLCSP-100(4.4x4.4) · 4.40×4.40mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)
Showing 1–12 of 15 uncropped original figures for STM32WB55 / STM32WB35
P59 · p59_fig01EXACT PACKAGE
STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) — Figure 12. STM32WB55Vx WLCSP100 ballout(1)
Figure 12. STM32WB55Vx WLCSP100 ballout(1)
P82 · p82_fig01EXACT PACKAGE
STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) — Figure 16. Power supply scheme (all packages except UFBGA129 and WLCSP100)
Figure 16. Power supply scheme (all packages except UFBGA129 and WLCSP100)
P83 · p83_fig01EXACT PACKAGE
STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) — Figure 17. Power supply scheme (UFBGA129 and WLCSP100 packages)
Figure 17. Power supply scheme (UFBGA129 and WLCSP100 packages)
P171 · p171_fig01EXACT PACKAGE
STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) — Figure 39. UFBGA129 recommended footprint
Figure 39. UFBGA129 recommended footprint
P175 · p175_fig01EXACT PACKAGE
STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) — Figure 42. WLCSP100 recommended footprint
Figure 42. WLCSP100 recommended footprint
P1 · p01_fig01881×760px
STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) — STM32WB55xx STM32WB35xx Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4
STM32WB55xx STM32WB35xx Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4
P58 · p58_fig011546×953px
STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) — Figure 10. STM32WB55Cx and STM32WB35Cx UFQFPN48 pinout(1)(2)
Figure 10. STM32WB55Cx and STM32WB35Cx UFQFPN48 pinout(1)(2)
P58 · p58_fig021546×1136px
STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) — Figure 11. STM32WB55Rx VFQFPN68 pinout(1)(2)
Figure 11. STM32WB55Rx VFQFPN68 pinout(1)(2)
P59 · p59_fig021751×1225px
STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) — Figure 13. STM32WB55Vx UFBGA129 ballout(1)
Figure 13. STM32WB55Vx UFBGA129 ballout(1)
P59 · p59_fig01P59
STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) — Datasheet Page 59 (p59_fig01)
Datasheet Page 59 (p59_fig01)
P82 · p82_fig01P82
STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) — Datasheet Page 82 (p82_fig01)
Datasheet Page 82 (p82_fig01)
P152 · p152_fig011546×641px
STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) — Figure 30. Typical connection diagram using the ADC
Figure 30. Typical connection diagram using the ADC
Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (STM32WB55VCY7TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) is a 100-pin embedded microcontroller unit (mcu) featuring a 4.40 × 4.40 × 0.59 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, UART, SPI, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
70 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
4.40 × 4.40 × 0.59 mm (A1=0.18 mm)
Package family: WLCSP (WLCSP-100(4.4x4.4))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, UART, SPI, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3 BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-100(4.4x4.4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.40 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=0.59mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-100(4.4x4.4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32WB55VCY7TR (WLCSP-100(4.4x4.4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32WB55VCY7TR (WLCSP-100(4.4x4.4))?

Manufactured by ST, the STM32WB55VCY7TR is housed in a WLCSP-100(4.4x4.4) package with 100 pins and a 0.40 mm lead pitch. Key pins include: A1 (PA11: Multiplexed I/O & Peripheral Pin PA11 (USB, SPI, PWM)), A2 (PA12: Multiplexed I/O & Peripheral Pin PA12 (UART)), A3 (PA14 (JTCK SWCLK)_: Multiplexed I/O & Peripheral Pin PA14 (JTCK SWCLK)_ (I2C, SWD/JTAG)), A4 (PA15 (JTDI): Multiplexed I/O & Peripheral Pin PA15 (JTDI) (SPI, SWD/JTAG)), A5 (PA13 (JTMS SWDIO)_: Multiplexed I/O & Peripheral Pin PA13 (JTMS SWDIO)_ (USB, SWD/JTAG)), A6 (PC10: Multiplexed I/O & Peripheral Pin PC10 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32WB55VCY7TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32WB55VCY7TR (WLCSP-100(4.4x4.4)) has a nominal body envelope of 4.40 × 4.40 mm, pitch e = 0.40 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32WB55VCY7TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32WB55VCY7TR (ST, WLCSP-100(4.4x4.4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32WB55 / STM32WB35 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOUSART1CTS. Supported peripheral buses: USB, SPI, PWM.
A2PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART.
A3PA14 (JTCK SWCLK)_Digital_IOSignal terminal PA14 (JTCK SWCLK)_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14 (JTCK SWCLK)_. Supported peripheral buses: I2C, SWD/JTAG.
A4PA15 (JTDI)Digital_IOSignal terminal PA15 (JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS_TSCG3IO1. Supported peripheral buses: SPI, SWD/JTAG.
A5PA13 (JTMS SWDIO)_Digital_IOSignal terminal PA13 (JTMS SWDIO)_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (JTMS SWDIO)_. Supported peripheral buses: USB, SWD/JTAG.
A6PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
A7PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
A8PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
A9PB3 (JTDO)Digital_IOSignal terminal PB3 (JTDO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB3 (JTDO). Supported peripheral buses: UART, PWM, SWD/JTAG.
A10VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B3VDDUSBPower_InPrimary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B4PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: USB, SPI.
B5PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: USB, I2C.
B6PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
B7PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
B8PD12Digital_IOSignal terminal PD12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD12. Supported peripheral buses: General.
B9VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B10PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
C1PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKLPUART1CTS. Supported peripheral buses: SPI, PWM.
C2PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKSPI2MISO. Supported peripheral buses: SPI.
C3PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKCM4EVENTOUT. Supported peripheral buses: SPI.
C4PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSSCM4EVENTOUT. Supported peripheral buses: SPI.
C5PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: RTC/CLK.
C6PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: I2C.
C7PB4 (NJTRST)Digital_IOSignal terminal PB4 (NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA, SPI1_MISOUSART1CTS. Supported peripheral buses: SPI, I2C, SWD/JTAG.
C8PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
C9PD13Digital_IOSignal terminal PD13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: General.
C10VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D1VDDSMPSPower_InPrimary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D2PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
D3PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI_TSCG5IO1. Supported peripheral buses: SPI.
D4PD8Digital_IOSignal terminal PD8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD8. Supported peripheral buses: General.
D5PD9Digital_IOSignal terminal PD9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD9. Supported peripheral buses: General.
D6PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSIUSART1CK. Supported peripheral buses: SPI.
D7PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: I2C.
D8PD14Digital_IOSignal terminal PD14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: PWM.
D9PC15 - OSC32_OUTDigital_IOSignal terminal PC15 - OSC32_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15 - OSC32_OUT. Supported peripheral buses: RTC/CLK.
D10PC14 - OSC32_INDigital_IOSignal terminal PC14 - OSC32_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN. Supported peripheral buses: RTC/CLK.
E1VLXSMPSDigital_IOSignal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General.
E2PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO_TSCG1IO3. Supported peripheral buses: SPI, PWM.
E3PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
E4PD10Digital_IOSignal terminal PD10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD10. Supported peripheral buses: General.
E5PD11Digital_IOSignal terminal PD11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD11. Supported peripheral buses: General.
E6PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
E7PD15Digital_IOSignal terminal PD15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: PWM.
E8PH3 BOOT0 -Digital_IOSignal terminal PH3 BOOT0 - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH3 BOOT0 -. Supported peripheral buses: General.
E9PH1Digital_IOSignal terminal PH1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1. Supported peripheral buses: General.
E10PH0Digital_IOSignal terminal PH0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0. Supported peripheral buses: General.
F1VSSSMPSGND0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
F2VFBSMPSDigital_IOSignal terminal VFBSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VFBSMPS. Supported peripheral buses: General.
F3PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI_TSCG1IO4. Supported peripheral buses: SPI, RTC/CLK.
F4PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
F5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART.
F6PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
F7PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: PWM.
F8PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
F9NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
F10PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: I2C.
G1PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
G2PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
G3PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSSLPUART1RTS. Supported peripheral buses: SPI.
G4PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General.
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