![CH549F (QFN-28-EP(4x4)) — 由Pn_MOD_OC[x]和Pn_DIR_PU[x]组合实现Pn 端口的相关配置，具体如下。](/api/v1/assets/C367229/extracted/figures/p27_fig01.png)
![CH549F (QFN-28-EP(4x4)) — 图10.2.1 I/O 引脚等效原理图 bPn_MOD_OC[x]](/api/v1/assets/C367229/extracted/figures/p28_fig01.png)
SOP-16 · 16P
Synchronized Pinout (Symbol / 2D / 3D) (29/29)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | 0 | I/O | Multiplexed I/O & Peripheral Pin 0 (General) |
| 2 | P1.7/SCK/TXD1_/AIN7 | I/O | Multiplexed I/O & Peripheral Pin P1.7/SCK/TXD1_/AIN7 (UART, SPI, ADC) |
| 3 | P5.7/RST | I/O | Multiplexed I/O & Peripheral Pin P5.7/RST (General) |
| 4 | P3.0/RXD | I/O | Multiplexed I/O & Peripheral Pin P3.0/RXD (UART) |
| 5 | P3.1/TXD | I/O | Multiplexed I/O & Peripheral Pin P3.1/TXD (UART) |
| 6 | P3.2/INT0 | I/O | Multiplexed I/O & Peripheral Pin P3.2/INT0 (General) |
| 7 | P3.3/INT1 | I/O | Multiplexed I/O & Peripheral Pin P3.3/INT1 (General) |
| 8 | P3.4/T0 | I/O | Multiplexed I/O & Peripheral Pin P3.4/T0 (General) |
| 9 | P3.5/T1 | I/O | Multiplexed I/O & Peripheral Pin P3.5/T1 (General) |
| 10 | P4.6/XI | I/O | Multiplexed I/O & Peripheral Pin P4.6/XI (RTC/CLK) |
| 11 | XO | I/O | Multiplexed I/O & Peripheral Pin XO (RTC/CLK) |
| 12 | P2.2/PWM3/INT0_ | I/O | Multiplexed I/O & Peripheral Pin P2.2/PWM3/INT0_ (PWM) |
| 13 | P2.4/PWM1/T2_/CAP1_ | I/O | Multiplexed I/O & Peripheral Pin P2.4/PWM1/T2_/CAP1_ (PWM) |
| 14 | P2.6/PWM6/RXD1 | I/O | Multiplexed I/O & Peripheral Pin P2.6/PWM6/RXD1 (UART, PWM) |
| 15 | P2.7/PWM7/TXD1 | I/O | Multiplexed I/O & Peripheral Pin P2.7/PWM7/TXD1 (UART, PWM) |
| 16 | P5.5/HVOD | I/O | Multiplexed I/O & Peripheral Pin P5.5/HVOD (General) |
| 17 | P5.1/DP/UDP | I/O | Multiplexed I/O & Peripheral Pin P5.1/DP/UDP (General) |
| 18 | P5.0/DM/UDM | I/O | Multiplexed I/O & Peripheral Pin P5.0/DM/UDM (General) |
| 19 | P0.7/TXD3/AIN15 | I/O | Multiplexed I/O & Peripheral Pin P0.7/TXD3/AIN15 (UART, ADC) |
| 20 | P0.6/RXD3/AIN14 | I/O | Multiplexed I/O & Peripheral Pin P0.6/RXD3/AIN14 (UART, ADC) |
| 21 | P0.5/TXD2/AIN13 | I/O | Multiplexed I/O & Peripheral Pin P0.5/TXD2/AIN13 (UART, ADC) |
| 22 | P0.4/RXD2/AIN12 | I/O | Multiplexed I/O & Peripheral Pin P0.4/RXD2/AIN12 (UART, ADC) |
| 23 | VDD | Power | Power Supply Input (VDD — 3.3V / 5.0V Standard Logic) |
| 24 | V33 | Power | Power Supply Input (V33 — 3.3V / 5.0V Standard Logic) |
| 25 | P1.0/T2/CAP1/AIN0 | I/O | Multiplexed I/O & Peripheral Pin P1.0/T2/CAP1/AIN0 (ADC) |
| 26 | P1.1/T2EX/CAP2/AIN1 | I/O | Multiplexed I/O & Peripheral Pin P1.1/T2EX/CAP2/AIN1 (ADC) |
| 27 | P1.4/SCS/UCC1/AIN4 | I/O | Multiplexed I/O & Peripheral Pin P1.4/SCS/UCC1/AIN4 (ADC) |
| 28 | IO33 | I/O | GPIO33 / FSPIHD / SUBSPIHD / SPIIO4 |
| 29 | GND | GND | Ground Reference Pin (GND) |
PIN 1 0
I/OMultiplexed I/O & Peripheral Pin 0 (General)
Design note: 输出系统主频的4 分频时钟信号 ，即Fsys/4
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
QFN-28-EP(4x4) · 4.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CH549
P66 · p66_fig01EXACT PACKAGE
P66 · p66_fig02EXACT PACKAGE
P1 · p01_fig011717×914px
P22 · p22_fig011757×1798px
P22 · p22_fig01P22
P27 · p27_fig011757×490px
P28 · p28_fig011678×1028px
P64 · p64_fig011757×2757px
P65 · p65_fig011757×1816px
Technical Specifications & Part Details (CH549F)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH549F (QFN-28-EP(4x4)) is a 28-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
40MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-28-EP(4x4))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol29 auto-grouped pins
IPC-7351B Land Pattern29 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteEPAD 2.56×2.56mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH549 (3)
QFN-28-EP(4x4) · 29P
LQFP-48(7x7) · 48P
Mechanical Dimensions & Land Pattern (QFN-28-EP(4x4))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-28-EP(4x4) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH549F (QFN-28-EP(4x4))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH549F (QFN-28-EP(4x4))?
Manufactured by WCH, the CH549F is housed in a QFN-28-EP(4x4) package with 29 pins and a 0.50 mm lead pitch. Key pins include: 1 (0: Multiplexed I/O & Peripheral Pin 0 (General)), 2 (P1.7/SCK/TXD1_/AIN7: Multiplexed I/O & Peripheral Pin P1.7/SCK/TXD1_/AIN7 (UART, SPI, ADC)), 3 (P5.7/RST: Multiplexed I/O & Peripheral Pin P5.7/RST (General)), 4 (P3.0/RXD: Multiplexed I/O & Peripheral Pin P3.0/RXD (UART)), 5 (P3.1/TXD: Multiplexed I/O & Peripheral Pin P3.1/TXD (UART)), 6 (P3.2/INT0: Multiplexed I/O & Peripheral Pin P3.2/INT0 (General)).
What are the IPC-7351B PCB Footprint dimensions for CH549F?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH549F (QFN-28-EP(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 2.56 × 2.56 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH549F?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH549F (WCH, QFN-28-EP(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (29 pins) & CH549 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | 0 | Digital_IO | Signal terminal 0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: 0. Supported peripheral buses: General. |
| 2 | P1.7/SCK/TXD1_/AIN7 | Digital_IO | Signal terminal P1.7/SCK/TXD1_/AIN7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: UART, SPI, ADC. |
| 3 | P5.7/RST | Digital_IO | Signal terminal P5.7/RST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.7/RST. Supported peripheral buses: General. |
| 4 | P3.0/RXD | Digital_IO | Signal terminal P3.0/RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.0/RXD. Supported peripheral buses: UART. |
| 5 | P3.1/TXD | Digital_IO | Signal terminal P3.1/TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.1/TXD. Supported peripheral buses: UART. |
| 6 | P3.2/INT0 | Digital_IO | Signal terminal P3.2/INT0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.2/INT0. Supported peripheral buses: General. |
| 7 | P3.3/INT1 | Digital_IO | Signal terminal P3.3/INT1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.3/INT1. Supported peripheral buses: General. |
| 8 | P3.4/T0 | Digital_IO | Signal terminal P3.4/T0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.4/T0. Supported peripheral buses: General. |
| 9 | P3.5/T1 | Digital_IO | Signal terminal P3.5/T1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.5/T1. Supported peripheral buses: General. |
| 10 | P4.6/XI | Digital_IO | Signal terminal P4.6/XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.6/XI. Supported peripheral buses: RTC/CLK. |
| 11 | XO | Digital_IO | Signal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK. |
| 12 | P2.2/PWM3/INT0_ | Digital_IO | Signal terminal P2.2/PWM3/INT0_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.2/PWM3/INT0_. Supported peripheral buses: PWM. |
| 13 | P2.4/PWM1/T2_/CAP1_ | Digital_IO | Signal terminal P2.4/PWM1/T2_/CAP1_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.4/PWM1/T2_/CAP1_. Supported peripheral buses: PWM. |
| 14 | P2.6/PWM6/RXD1 | Digital_IO | Signal terminal P2.6/PWM6/RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.6/PWM6/RXD1. Supported peripheral buses: UART, PWM. |
| 15 | P2.7/PWM7/TXD1 | Digital_IO | Signal terminal P2.7/PWM7/TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.7/PWM7/TXD1. Supported peripheral buses: UART, PWM. |
| 16 | P5.5/HVOD | Digital_IO | Signal terminal P5.5/HVOD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.5/HVOD. Supported peripheral buses: General. |
| 17 | P5.1/DP/UDP | Digital_IO | Signal terminal P5.1/DP/UDP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.1/DP/UDP. Supported peripheral buses: General. |
| 18 | P5.0/DM/UDM | Digital_IO | Signal terminal P5.0/DM/UDM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.0/DM/UDM. Supported peripheral buses: General. |
| 19 | P0.7/TXD3/AIN15 | Digital_IO | Signal terminal P0.7/TXD3/AIN15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.7/TXD3/AIN15. Supported peripheral buses: UART, ADC. |
| 20 | P0.6/RXD3/AIN14 | Digital_IO | Signal terminal P0.6/RXD3/AIN14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.6/RXD3/AIN14. Supported peripheral buses: UART, ADC. |
| 21 | P0.5/TXD2/AIN13 | Digital_IO | Signal terminal P0.5/TXD2/AIN13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.5/TXD2/AIN13. Supported peripheral buses: UART, ADC. |
| 22 | P0.4/RXD2/AIN12 | Digital_IO | Signal terminal P0.4/RXD2/AIN12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.4/RXD2/AIN12. Supported peripheral buses: UART, ADC. |
| 23 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 24 | V33 | Power_In | Primary positive power supply input (V33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 25 | P1.0/T2/CAP1/AIN0 | Analog | Signal terminal P1.0/T2/CAP1/AIN0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.0/T2/CAP1/AIN0. Supported peripheral buses: ADC. |
| 26 | P1.1/T2EX/CAP2/AIN1 | Analog | Signal terminal P1.1/T2EX/CAP2/AIN1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.1/T2EX/CAP2/AIN1. Supported peripheral buses: ADC. |
| 27 | P1.4/SCS/UCC1/AIN4 | Analog | Signal terminal P1.4/SCS/UCC1/AIN4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.4/SCS/UCC1/AIN4. Supported peripheral buses: ADC. |
| 28 | IO33 | Digital_IO | GPIO33 / FSPIHD / SUBSPIHD / SPIIO4 |
| 29 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |