ChipDocs.org
⌘K
2284 PARTSUpload PDF
CH392F (QFN-28-EP(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH392F

WCHID: C2886218QFN-28-EP(4x4) · 29 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH392F (QFN-28-EP(4x4))1RSTI2SEL3VCC4VCC5VDD6RXD7TXD8RXP9RXN10TXP11TXN12INT13NC14ANT15LINK29EP28CSS27SCK26SDI25SDO24NC23SEL22VCC21NC20VREF19XI18XO17NC16RSTIGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.225.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829E=4.00mm · Pitch e=0.40mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RSTII/OMultiplexed I/O & Peripheral Pin RSTI (General)
2SELI/OMultiplexed I/O & Peripheral Pin SEL (SPI)
3VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
4VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
5VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
6RXDI/OMultiplexed I/O & Peripheral Pin RXD (UART)
7TXDI/OMultiplexed I/O & Peripheral Pin TXD (UART)
8RXPI/OMultiplexed I/O & Peripheral Pin RXP (General)
9RXNI/OMultiplexed I/O & Peripheral Pin RXN (General)
10TXPI/OMultiplexed I/O & Peripheral Pin TXP (General)
11TXNI/OMultiplexed I/O & Peripheral Pin TXN (General)
12INTI/OMultiplexed I/O & Peripheral Pin INT (General)
13NCI/OMultiplexed I/O & Peripheral Pin NC (General)
14ANTI/OMultiplexed I/O & Peripheral Pin ANT (General)
15LINKI/OMultiplexed I/O & Peripheral Pin LINK (General)
16RSTII/OMultiplexed I/O & Peripheral Pin RSTI (General)
17NCI/OMultiplexed I/O & Peripheral Pin NC (General)
18XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
19XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
20VREFAnalogMultiplexed I/O & Peripheral Pin VREF (General)
21NCI/OMultiplexed I/O & Peripheral Pin NC (General)
22VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
23SELI/OMultiplexed I/O & Peripheral Pin SEL (SPI)
24NCI/OMultiplexed I/O & Peripheral Pin NC (General)
25SDOI/OMultiplexed I/O & Peripheral Pin SDO (General)
26SDII/OMultiplexed I/O & Peripheral Pin SDI (General)
27SCKI/OMultiplexed I/O & Peripheral Pin SCK (SPI)
28CSSI/OMultiplexed I/O & Peripheral Pin CSS (General)
29EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 RSTI
I/O
Multiplexed I/O & Peripheral Pin RSTI (General)
Design note: 外部复位输入 低电平有效 ，
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH392F (WCH · QFN-28-EP(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH392F (QFN-28-EP(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH392F (QFN-28-EP(4x4)) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH392F (QFN-28-EP(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH392F (QFN-28-EP(4x4)) - 4. Package Dimensions (D×E×A)
QFN-28-EP(4x4) · 4.00×4.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH392F (QFN-28-EP(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH392F (QFN-28-EP(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH392
P2 · p02_fig02EXACT PACKAGE
CH392F (QFN-28-EP(4x4)) — RSTI 1 | SEL 2 | TXD 3 | RXD 4 | SCS 5 | SCK 6 | SDO 7 | SDI 8 | RXP 9 | RXN 10 TXP 11 TXN 12 NC 13 VDD 14 INT 15 ACT 16 LINK 17 GND 18 XI 19 XO 20 | CH392T(TSSOP20) CH392F(QFN28) 封装形式 塑体尺寸 引脚间距 封装说明 订货型号 TSSOP20 4.4*6.5mm 0.65mm 25.6mil 薄小
RSTI 1 | SEL 2 | TXD 3 | RXD 4 | SCS 5 | SCK 6 | SDO 7 | SDI 8 | RXP 9 | RXN 10 TXP 11 TXN 12 NC 13 VDD 14 INT 15 ACT 16 LINK 17 GND 18 XI 19 XO 20 | CH392T(TSSOP20) CH392F(QFN28) 封装形式 塑体尺寸 引脚间距 封装说明 订货型号 TSSOP20 4.4*6.5mm 0.65mm 25.6mil 薄小
P1 · p01_fig011746×1240px
CH392F (QFN-28-EP(4x4)) — 2、特点
2、特点
P2 · p02_fig01578×598px
CH392F (QFN-28-EP(4x4)) — GND 0 | NC 1 | NC 2 | VCC 3 | VCC 4 | VDD 5 | RXD 6 | TXD 7 | RXP 8 RXN 9 TXP 10 TXN 11 INT 12 NC 13 ACT 14 | LINK 15 RSTI 16 NC 17 XO 18 XI 19 VREF 20 NC 21 | VCC 22 | SEL 23 | NC 24 | SDO 25 | SDI 26 | SCK 27 | SCS 28 | CH392T(TSSOP20) CH
GND 0 | NC 1 | NC 2 | VCC 3 | VCC 4 | VDD 5 | RXD 6 | TXD 7 | RXP 8 RXN 9 TXP 10 TXN 11 INT 12 NC 13 ACT 14 | LINK 15 RSTI 16 NC 17 XO 18 XI 19 VREF 20 NC 21 | VCC 22 | SEL 23 | NC 24 | SDO 25 | SDI 26 | SCK 27 | SCS 28 | CH392T(TSSOP20) CH
P2 · p02_fig01P2
CH392F (QFN-28-EP(4x4)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P24 · p24_fig011166×1032px
CH392F (QFN-28-EP(4x4)) — TCP 和UDP 是两种比较重要的传输层协议，两者都使用IP 作为网络层协议。 TCP 是一种面向连接的传输，能够提供可靠的字节流传输服务。 UDP 是一种简单的面向数据报的运输层协议，与TCP 不同的是UDP 无法保证数据报文准确达到 目的地。
TCP 和UDP 是两种比较重要的传输层协议，两者都使用IP 作为网络层协议。 TCP 是一种面向连接的传输，能够提供可靠的字节流传输服务。 UDP 是一种简单的面向数据报的运输层协议，与TCP 不同的是UDP 无法保证数据报文准确达到 目的地。
P27 · p27_fig011513×1027px
CH392F (QFN-28-EP(4x4)) — 8.3. 硬件电路设计 | 8.3.1. CH392T 硬件电路设计 | 3V3 | C2 0.1uF | RST | ERXP ERXN | UART_TX UART_RX SPI_CS SPI_SCK SPI_MISO SPI_MOSI | SEL | TX+ 1 | TX- 2 | RX+ 3 | NC 4 | NC 5 | RX- 6 | NC 7 | NC 8 | P1 RJ45 | TDP 1 | TD 2 | TDN 3 | RDP 6 | RD 7 | RDN
8.3. 硬件电路设计 | 8.3.1. CH392T 硬件电路设计 | 3V3 | C2 0.1uF | RST | ERXP ERXN | UART_TX UART_RX SPI_CS SPI_SCK SPI_MISO SPI_MOSI | SEL | TX+ 1 | TX- 2 | RX+ 3 | NC 4 | NC 5 | RX- 6 | NC 7 | NC 8 | P1 RJ45 | TDP 1 | TD 2 | TDN 3 | RDP 6 | RD 7 | RDN
P28 · p28_fig011516×1458px
CH392F (QFN-28-EP(4x4)) — CH392F已内置了晶体X1的部分振荡电容，C7和C8可以根据晶体参数调节。对于负载电容为12pF 的X1，无需C7和C8；对于负载电容为20pF的X1，C7和C8建议各15pF。
CH392F已内置了晶体X1的部分振荡电容，C7和C8可以根据晶体参数调节。对于负载电容为12pF 的X1，无需C7和C8；对于负载电容为20pF的X1，C7和C8建议各15pF。
P28 · p28_fig01P28
CH392F (QFN-28-EP(4x4)) — Datasheet Page 28 (p28_fig01)
Datasheet Page 28 (p28_fig01)

Technical Specifications & Part Details (CH392F)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH392F (QFN-28-EP(4x4)) is a 28-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-28-EP(4x4))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 2.40×2.40mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — CH392 (2)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (QFN-28-EP(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-28-EP(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH392F (QFN-28-EP(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH392F (QFN-28-EP(4x4))?

Manufactured by WCH, the CH392F is housed in a QFN-28-EP(4x4) package with 29 pins and a 0.40 mm lead pitch. Key pins include: 1 (RSTI: Multiplexed I/O & Peripheral Pin RSTI (General)), 2 (SEL: Multiplexed I/O & Peripheral Pin SEL (SPI)), 3 (VCC: Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)), 4 (VCC: Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)), 5 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), 6 (RXD: Multiplexed I/O & Peripheral Pin RXD (UART)).

What are the IPC-7351B PCB Footprint dimensions for CH392F?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH392F (QFN-28-EP(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.40 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 2.40 × 2.40 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH392F?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH392F (WCH, QFN-28-EP(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & CH392 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RSTIDigital_IOSignal terminal RSTI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSTI. Supported peripheral buses: General.
2SELDigital_IOSignal terminal SEL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEL. Supported peripheral buses: SPI.
3VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
5VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
6RXDDigital_IOSignal terminal RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART.
7TXDDigital_IOSignal terminal TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
8RXPDigital_IOSignal terminal RXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXP. Supported peripheral buses: General.
9RXNDigital_IOSignal terminal RXN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXN. Supported peripheral buses: General.
10TXPDigital_IOSignal terminal TXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXP. Supported peripheral buses: General.
11TXNDigital_IOSignal terminal TXN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXN. Supported peripheral buses: General.
12INTDigital_IOSignal terminal INT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT. Supported peripheral buses: General.
13NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
14ANTRF_50OhmSignal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General.
15LINKDigital_IOSignal terminal LINK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LINK. Supported peripheral buses: General.
16RSTIDigital_IOSignal terminal RSTI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSTI. Supported peripheral buses: General.
17NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
18XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
19XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
20VREFAnalogSignal terminal VREF (Analog, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VREF. Supported peripheral buses: General.
21NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
22VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
23SELDigital_IOSignal terminal SEL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEL. Supported peripheral buses: SPI.
24NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
25SDODigital_IOSignal terminal SDO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDO. Supported peripheral buses: General.
26SDIDigital_IOSignal terminal SDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDI. Supported peripheral buses: General.
27SCKDigital_IOSignal terminal SCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCK. Supported peripheral buses: SPI.
28CSSDigital_IOSignal terminal CSS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CSS. Supported peripheral buses: General.
29EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
ExplorePartsPackagesMFRsUpload