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CH392T (TSSOP-20) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH392T

WCHID: C39831290TSSOP-20 · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH392T (TSSOP-20)1RSTI2SEL3TXD4RXD5SCS6SCK7SDO8SDI9RXP10RXN20XO19XI18GND17LINK16ACT15INT14VDD13NC12TXN11TXPGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.217.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=4.40mm · Pitch e=0.65mmD=6.50mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 4.40mm × 6.50mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RSTII/OMultiplexed I/O & Peripheral Pin RSTI (General)
2SELI/OMultiplexed I/O & Peripheral Pin SEL (SPI)
3TXDI/OMultiplexed I/O & Peripheral Pin TXD (UART)
4RXDI/OMultiplexed I/O & Peripheral Pin RXD (UART)
5SCSI/OMultiplexed I/O & Peripheral Pin SCS (General)
6SCKI/OMultiplexed I/O & Peripheral Pin SCK (SPI)
7SDOI/OMultiplexed I/O & Peripheral Pin SDO (General)
8SDII/OMultiplexed I/O & Peripheral Pin SDI (General)
9RXPI/OMultiplexed I/O & Peripheral Pin RXP (General)
10RXNI/OMultiplexed I/O & Peripheral Pin RXN (General)
11TXPI/OMultiplexed I/O & Peripheral Pin TXP (General)
12TXNI/OMultiplexed I/O & Peripheral Pin TXN (General)
13NCI/OMultiplexed I/O & Peripheral Pin NC (General)
14VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
15INTI/OMultiplexed I/O & Peripheral Pin INT (General)
16ACTI/OMultiplexed I/O & Peripheral Pin ACT (General)
17LINKI/OMultiplexed I/O & Peripheral Pin LINK (General)
18GNDGNDGround Reference Pin (GND)
19XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
20XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
PIN 1 RSTI
I/O
Multiplexed I/O & Peripheral Pin RSTI (General)
Design note: 外部复位输入 低电平有效 ，
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH392T (WCH · TSSOP-20)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH392T (TSSOP-20) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH392T (TSSOP-20) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH392T (TSSOP-20) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH392T (TSSOP-20) - 4. Package Dimensions (D×E×A)
TSSOP-20 · 4.40×6.50mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH392T (TSSOP-20) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH392T (TSSOP-20) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for CH392
P1 · p01_fig011746×1240px
CH392T (TSSOP-20) — 2、特点
2、特点
P2 · p02_fig011459×645px
CH392T (TSSOP-20) — CH392 手册 https://wch.cn
CH392 手册 https://wch.cn
P2 · p02_fig01P2
CH392T (TSSOP-20) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P24 · p24_fig011166×1032px
CH392T (TSSOP-20) — TCP 和UDP 是两种比较重要的传输层协议，两者都使用IP 作为网络层协议。 TCP 是一种面向连接的传输，能够提供可靠的字节流传输服务。 UDP 是一种简单的面向数据报的运输层协议，与TCP 不同的是UDP 无法保证数据报文准确达到 目的地。
TCP 和UDP 是两种比较重要的传输层协议，两者都使用IP 作为网络层协议。 TCP 是一种面向连接的传输，能够提供可靠的字节流传输服务。 UDP 是一种简单的面向数据报的运输层协议，与TCP 不同的是UDP 无法保证数据报文准确达到 目的地。
P27 · p27_fig011513×1028px
CH392T (TSSOP-20) — 8.3. 硬件电路设计 | 8.3.1. CH392T 硬件电路设计 | 3V3 | C2 0.1uF | RST | ERXP ERXN | UART_TX UART_RX SPI_CS SPI_SCK SPI_MISO SPI_MOSI | SEL | TX+ 1 | TX- 2 | RX+ 3 | NC 4 | NC 5 | RX- 6 | NC 7 | NC 8 | P1 RJ45 | TDP 1 | TD 2 | TDN 3 | RDP 6 | RD 7 | RDN
8.3. 硬件电路设计 | 8.3.1. CH392T 硬件电路设计 | 3V3 | C2 0.1uF | RST | ERXP ERXN | UART_TX UART_RX SPI_CS SPI_SCK SPI_MISO SPI_MOSI | SEL | TX+ 1 | TX- 2 | RX+ 3 | NC 4 | NC 5 | RX- 6 | NC 7 | NC 8 | P1 RJ45 | TDP 1 | TD 2 | TDN 3 | RDP 6 | RD 7 | RDN
P28 · p28_fig011516×1458px
CH392T (TSSOP-20) — CH392 手册 https://wch.cn
CH392 手册 https://wch.cn
P28 · p28_fig01P28
CH392T (TSSOP-20) — Datasheet Page 28 (p28_fig01)
Datasheet Page 28 (p28_fig01)

Technical Specifications & Part Details (CH392T)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH392T (TSSOP-20) is a 20-pin standard electronic & interconnect component featuring a 6.50 × 4.40 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.50 × 4.40 × 1.00 mm (A1=0.10 mm)
Package family: TSSOP (TSSOP-20)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TSSOP-20)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.50 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.45 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TSSOP-20
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH392T (TSSOP-20)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH392T (TSSOP-20)?

Manufactured by WCH, the CH392T is housed in a TSSOP-20 package with 20 pins and a 0.65 mm lead pitch. Key pins include: 1 (RSTI: Multiplexed I/O & Peripheral Pin RSTI (General)), 2 (SEL: Multiplexed I/O & Peripheral Pin SEL (SPI)), 3 (TXD: Multiplexed I/O & Peripheral Pin TXD (UART)), 4 (RXD: Multiplexed I/O & Peripheral Pin RXD (UART)), 5 (SCS: Multiplexed I/O & Peripheral Pin SCS (General)), 6 (SCK: Multiplexed I/O & Peripheral Pin SCK (SPI)).

What are the IPC-7351B PCB Footprint dimensions for CH392T?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH392T (TSSOP-20) has a nominal body envelope of 4.40 × 6.50 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH392T?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH392T (WCH, TSSOP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & CH392 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RSTIDigital_IOSignal terminal RSTI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSTI. Supported peripheral buses: General.
2SELDigital_IOSignal terminal SEL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEL. Supported peripheral buses: SPI.
3TXDDigital_IOSignal terminal TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
4RXDDigital_IOSignal terminal RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART.
5SCSDigital_IOSignal terminal SCS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCS. Supported peripheral buses: General.
6SCKDigital_IOSignal terminal SCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCK. Supported peripheral buses: SPI.
7SDODigital_IOSignal terminal SDO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDO. Supported peripheral buses: General.
8SDIDigital_IOSignal terminal SDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDI. Supported peripheral buses: General.
9RXPDigital_IOSignal terminal RXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXP. Supported peripheral buses: General.
10RXNDigital_IOSignal terminal RXN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXN. Supported peripheral buses: General.
11TXPDigital_IOSignal terminal TXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXP. Supported peripheral buses: General.
12TXNDigital_IOSignal terminal TXN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXN. Supported peripheral buses: General.
13NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
14VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
15INTDigital_IOSignal terminal INT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT. Supported peripheral buses: General.
16ACTDigital_IOSignal terminal ACT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ACT. Supported peripheral buses: General.
17LINKDigital_IOSignal terminal LINK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LINK. Supported peripheral buses: General.
18GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
19XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
20XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
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