ChipDocs.org
⌘K
2284 PARTSUpload PDF
CH342F (QFN-24-EP(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH342F

WCHID: C2841530QFN-24-EP(4x4) · 25 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH342F (QFN-24-EP(4x4))1RI02GND3UD+4UD -5VIO6V37VDD58VBUS9RST10CTS111RTS112RXD113TXD125EP24DCD023DTR022DSR021TXD020GND19RTS018CTS017RI116DCD115DTR114DSR1Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.222.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425E=4.00mm · Pitch e=0.50mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (25/25)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RI0I/OMultiplexed I/O & Peripheral Pin RI0 (General)
2GNDGNDGround Reference Pin (GND)
3UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
4UD -I/OMultiplexed I/O & Peripheral Pin UD - (General)
5VIOI/OMultiplexed I/O & Peripheral Pin VIO (General)
6V3PowerRegulated Power Output (V3 — 3.3V / 5.0V Standard Logic)
7VDD5PowerPower Supply Input (VDD5 — 3.3V / 5.0V Standard Logic)
8VBUSPowerPower Supply Input (VBUS — 3.3V / 5.0V Standard Logic)
9RSTI/OMultiplexed I/O & Peripheral Pin RST (General)
10CTS1I/OMultiplexed I/O & Peripheral Pin CTS1 (UART)
11RTS1I/OMultiplexed I/O & Peripheral Pin RTS1 (UART)
12RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
13TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
14DSR1I/OMultiplexed I/O & Peripheral Pin DSR1 (UART)
15DTR1I/OMultiplexed I/O & Peripheral Pin DTR1 (UART)
16DCD1I/OMultiplexed I/O & Peripheral Pin DCD1 (General)
17RI1I/OMultiplexed I/O & Peripheral Pin RI1 (General)
18CTS0I/OMultiplexed I/O & Peripheral Pin CTS0 (UART)
19RTS0I/OMultiplexed I/O & Peripheral Pin RTS0 (UART)
20GNDGNDGround Reference Pin (GND)
21TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
22DSR0I/OMultiplexed I/O & Peripheral Pin DSR0 (UART)
23DTR0I/OMultiplexed I/O & Peripheral Pin DTR0 (UART)
24DCD0I/OMultiplexed I/O & Peripheral Pin DCD0 (General)
25EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 RI0
I/O
Multiplexed I/O & Peripheral Pin RI0 (General)
Design note: Signal terminal RI0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI0. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH342F (WCH · QFN-24-EP(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH342F (QFN-24-EP(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH342F (QFN-24-EP(4x4)) - 2. Standard Pinout (Top View)
True package pinout (25 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH342F (QFN-24-EP(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH342F (QFN-24-EP(4x4)) - 4. Package Dimensions (D×E×A)
QFN-24-EP(4x4) · 4.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH342F (QFN-24-EP(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (25 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH342F (QFN-24-EP(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH342
P2 · p02_fig01EXACT PACKAGE
CH342F (QFN-24-EP(4x4)) — Package Width of Plastic Pitch of Pin Instruction of Package Ordering Information
Package Width of Plastic Pitch of Pin Instruction of Package Ordering Information
P1 · p01_fig011618×506px
CH342F (QFN-24-EP(4x4)) — 2. Features
2. Features
P2 · p02_fig01P2
CH342F (QFN-24-EP(4x4)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P9 · p09_fig01809×985px
CH342F (QFN-24-EP(4x4)) — CH342 Datasheet 9
CH342 Datasheet 9
P10 · p10_fig01899×663px
CH342F (QFN-24-EP(4x4)) — CH342 Datasheet 10
CH342 Datasheet 10
P10 · p10_fig021094×261px
CH342F (QFN-24-EP(4x4)) — 7.3. USB to dual RS485 UART (Figure below)
7.3. USB to dual RS485 UART (Figure below)
P10 · p10_fig03586×608px
CH342F (QFN-24-EP(4x4)) — vou RADE THD VDD THDA Pray GND —RIS8 4 Boot 22 U6 NCU REDL vou THD Tabd RED VDD RTSi ae aria _ #tet SFIO GND — GTR aria tt Ur NCuUZ
vou RADE THD VDD THDA Pray GND —RIS8 4 Boot 22 U6 NCU REDL vou THD Tabd RED VDD RTSi ae aria _ #tet SFIO GND — GTR aria tt Ur NCuUZ
P10 · p10_fig01P10
CH342F (QFN-24-EP(4x4)) — Datasheet Page 10 (p10_fig01)
Datasheet Page 10 (p10_fig01)

Technical Specifications & Part Details (CH342F)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH342F (QFN-24-EP(4x4)) is a 24-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 1.00 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 1.00 mm (A1=0.03 mm)
Package family: QFN (QFN-24-EP(4x4))
Pin Count & Lead PitchN / e
24 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol25 auto-grouped pins
OK
IPC-7351B Land Pattern25 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 2.56×2.56mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-24-EP(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
25P / 25Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-24-EP(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH342F (QFN-24-EP(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH342F (QFN-24-EP(4x4))?

Manufactured by WCH, the CH342F is housed in a QFN-24-EP(4x4) package with 25 pins and a 0.50 mm lead pitch. Key pins include: 1 (RI0: Multiplexed I/O & Peripheral Pin RI0 (General)), 2 (GND: Ground Reference Pin (GND)), 3 (UD+: Multiplexed I/O & Peripheral Pin UD+ (USB)), 4 (UD -: Multiplexed I/O & Peripheral Pin UD - (General)), 5 (VIO: Multiplexed I/O & Peripheral Pin VIO (General)), 6 (V3: Regulated Power Output (V3 — 3.3V / 5.0V Standard Logic)).

What are the IPC-7351B PCB Footprint dimensions for CH342F?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH342F (QFN-24-EP(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 25 copper pads plus a central exposed thermal pad (EPAD) of 2.56 × 2.56 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH342F?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH342F (WCH, QFN-24-EP(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (25 pins) & CH342 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RI0Digital_IOSignal terminal RI0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI0. Supported peripheral buses: General.
2GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
3UD+Digital_IOSignal terminal UD+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
4UD -Digital_IOSignal terminal UD - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD -. Supported peripheral buses: General.
5VIODigital_IOSignal terminal VIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO. Supported peripheral buses: General.
6V3Power_OutRegulated power output rail (V3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
7VDD5Power_InPrimary positive power supply input (VDD5) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
8VBUSPower_InPrimary positive power supply input (VBUS) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
9RSTDigital_IOSignal terminal RST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST. Supported peripheral buses: General.
10CTS1Digital_IOSignal terminal CTS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS1. Supported peripheral buses: UART.
11RTS1Digital_IOSignal terminal RTS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS1. Supported peripheral buses: UART.
12RXD1Digital_IOSignal terminal RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART.
13TXD1Digital_IOSignal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
14DSR1Digital_IOSignal terminal DSR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR1. Supported peripheral buses: UART.
15DTR1Digital_IOSignal terminal DTR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR1. Supported peripheral buses: UART.
16DCD1Digital_IOSignal terminal DCD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD1. Supported peripheral buses: General.
17RI1Digital_IOSignal terminal RI1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI1. Supported peripheral buses: General.
18CTS0Digital_IOSignal terminal CTS0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS0. Supported peripheral buses: UART.
19RTS0Digital_IOSignal terminal RTS0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS0. Supported peripheral buses: UART.
20GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
21TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
22DSR0Digital_IOSignal terminal DSR0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR0. Supported peripheral buses: UART.
23DTR0Digital_IOSignal terminal DTR0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR0. Supported peripheral buses: UART.
24DCD0Digital_IOSignal terminal DCD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD0. Supported peripheral buses: General.
25EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
ExplorePartsPackagesMFRsUpload