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STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32WB05KZV6TR

STID: C28314403VFQFPN-32-EP(5x5) · 33 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32WB05KZV6TR (VFQFPN-32-EP(5x5))1PB32PB23PB14PB05PA36PA27PA18PA09PA810PA911PA1012PA1113VDD214RF115VDDRF16OSCOUT17OSCIN33GND32VDD131PB430PB529RSTN28VDDA_VCAP27VFBSD26VSSSD25VLXSD24VDDSD23PB622PB721PB12/RCC_OSC20PB13/RCC_OSC19PB1418PB15Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.827.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233E=5.00mm · Pitch e=0.50mmD=5.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
2PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
3PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
4PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
5PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
6PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
7PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
8PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
9PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
10PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
11PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
12PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
13VDD2PowerPower Supply Input (VDD2 — 3.3V VDD (Max 4.0V))
14RF1I/OMultiplexed I/O & Peripheral Pin RF1 (General)
15VDDRFPowerPower Supply Input (VDDRF — 3.3V VDD (Max 4.0V))
16OSCOUTI/OMultiplexed I/O & Peripheral Pin OSCOUT (RTC/CLK)
17OSCINI/OMultiplexed I/O & Peripheral Pin OSCIN (RTC/CLK)
18PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
19PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
20PB13/RCC_OSC32_INI/OMultiplexed I/O & Peripheral Pin PB13/RCC_OSC32_IN (RTC/CLK)
21PB12/RCC_OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PB12/RCC_OSC32_OUT (RTC/CLK)
22PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
23PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
24VDDSDPowerPower Supply Input (VDDSD — 3.3V VDD (Max 4.0V))
25VLXSDI/OMultiplexed I/O & Peripheral Pin VLXSD (General)
26VSSSDGNDGround Reference Pin (VSSSD)
27VFBSDI/OMultiplexed I/O & Peripheral Pin VFBSD (General)
28VDDA_VCAPPowerPower Supply Input (VDDA_VCAP — 3.3V VDD (Max 4.0V))
29RSTNI/OMultiplexed I/O & Peripheral Pin RSTN (General)
30PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
31PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
32VDD1PowerPower Supply Input (VDD1 — 3.3V VDD (Max 4.0V))
33GNDGNDGround Reference Pin (GND)
PIN 1 PB3
I/O
Multiplexed I/O & Peripheral Pin PB3 (General)
Design note: Signal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32WB05KZV6TR (ST · VFQFPN-32-EP(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) - 2. Standard Pinout (Top View)
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) - 4. Package Dimensions (D×E×A)
VFQFPN-32-EP(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for STM32WB05
P1 · p01_fig02EXACT PACKAGE
STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) — VFQFPN32 5x5 mm
VFQFPN32 5x5 mm
P24 · p24_fig01EXACT PACKAGE
STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) — Figure 7. Pinout top view (VFQFPN32 package)
Figure 7. Pinout top view (VFQFPN32 package)
P29 · p29_fig02EXACT PACKAGE
STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) — Figure 10. Application circuit: DC-DC converter, VFQFPN32 package
Figure 10. Application circuit: DC-DC converter, VFQFPN32 package
P53 · p53_fig01EXACT PACKAGE
STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) — Figure 17. VFQFPN32 - Outline
Figure 17. VFQFPN32 - Outline
P54 · p54_fig01EXACT PACKAGE
STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) — A1 0 - 0.05 0 - 0.0020
A1 0 - 0.05 0 - 0.0020
P54 · p54_fig02EXACT PACKAGE
STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) — Figure 18. VFQFPN32 - Footprint example
Figure 18. VFQFPN32 - Footprint example
P1 · p01_fig01826×382px
STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) — Low Energy and 2.4 GHz radio solution
Low Energy and 2.4 GHz radio solution
P1 · p01_fig02P1
STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P12 · p12_fig011489×477px
STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) — Figure 4. Power supply configuration
Figure 4. Power supply configuration
P24 · p24_fig01P24
STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) — Datasheet Page 24 (p24_fig01)
Datasheet Page 24 (p24_fig01)
P29 · p29_fig011331×1101px
STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) — Figure 9. Application circuit: DC-DC converter, WLCSP36 package
Figure 9. Application circuit: DC-DC converter, WLCSP36 package
P29 · p29_fig02P29
STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) — Datasheet Page 29 (p29_fig02)
Datasheet Page 29 (p29_fig02)
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (STM32WB05KZV6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) is a 32-pin embedded microcontroller unit (mcu) featuring a 5.00 × 5.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, UART, SPI, I2C, I2S, ADC, JTAG / SWD, IrDA, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
2 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (VFQFPN-32-EP(5x5))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, UART, SPI, I2C, I2S, ADC, JTAG / SWD, IrDA, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol33 auto-grouped pins
OK
IPC-7351B Land Pattern33 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 3.50×3.50mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (VFQFPN-32-EP(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
VFQFPN-32-EP(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32WB05KZV6TR (VFQFPN-32-EP(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32WB05KZV6TR (VFQFPN-32-EP(5x5))?

Manufactured by ST, the STM32WB05KZV6TR is housed in a VFQFPN-32-EP(5x5) package with 33 pins and a 0.50 mm lead pitch. Key pins include: 1 (PB3: Multiplexed I/O & Peripheral Pin PB3 (General)), 2 (PB2: Multiplexed I/O & Peripheral Pin PB2 (General)), 3 (PB1: Multiplexed I/O & Peripheral Pin PB1 (General)), 4 (PB0: Multiplexed I/O & Peripheral Pin PB0 (General)), 5 (PA3: Multiplexed I/O & Peripheral Pin PA3 (General)), 6 (PA2: Multiplexed I/O & Peripheral Pin PA2 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32WB05KZV6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32WB05KZV6TR (VFQFPN-32-EP(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 3.50 × 3.50 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32WB05KZV6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32WB05KZV6TR (ST, VFQFPN-32-EP(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & STM32WB05 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
2PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
3PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
4PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
5PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
6PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
7PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
8PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
9PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
10PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
11PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
12PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
13VDD2Power_InPrimary positive power supply input (VDD2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
14RF1RF_50OhmSignal terminal RF1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: RF1. Supported peripheral buses: General.
15VDDRFPower_InPrimary positive power supply input (VDDRF) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
16OSCOUTDigital_IOSignal terminal OSCOUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSCOUT. Supported peripheral buses: RTC/CLK.
17OSCINDigital_IOSignal terminal OSCIN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSCIN. Supported peripheral buses: RTC/CLK.
18PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
19PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
20PB13/RCC_OSC32_INDigital_IOSignal terminal PB13/RCC_OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB13/RCC_OSC32_IN. Supported peripheral buses: RTC/CLK.
21PB12/RCC_OSC32_OUTDigital_IOSignal terminal PB12/RCC_OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB12/RCC_OSC32_OUT. Supported peripheral buses: RTC/CLK.
22PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
23PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
24VDDSDPower_InPrimary positive power supply input (VDDSD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
25VLXSDDigital_IOSignal terminal VLXSD (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSD. Supported peripheral buses: General.
26VSSSDGND0V electrical ground return terminal (VSSSD) for internal core logic, I/O drivers, and analog sub-blocks.
27VFBSDDigital_IOSignal terminal VFBSD (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VFBSD. Supported peripheral buses: General.
28VDDA_VCAPPower_InPrimary positive power supply input (VDDA_VCAP) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
29RSTNDigital_IOSignal terminal RSTN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: RSTN. Supported peripheral buses: General.
30PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
31PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
32VDD1Power_InPrimary positive power supply input (VDD1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
33GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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