![CH445P (QFN-16(3x3)) — D 6 =a] 7 1 a a TEE.](/api/v1/assets/C2683595/extracted/figures/p17_fig01.png)
![CH445P (QFN-16(3x3)) — 8.4. QFN16-3*3 [MSOP-10]](/api/v1/assets/C87711/extracted/package_dimensions.png)
SC-70-6(SOT-363) · 6P
IPC-7351B
6P2.0×1.2×0.95mmP=0.65mm
CH445 / CH448 / CH440 (SC-70-6(SOT-363))
Synchronized Pinout (Symbol / 2D / 3D) (17/17)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | IN | I/O | Multiplexed I/O & Peripheral Pin IN (General) |
| 2 | S1A S1B 、 、 S1C S1D 、 | I/O | Multiplexed I/O & Peripheral Pin S1A S1B 、 、 S1C S1D 、 (General) |
| 3 | S2A S2B 、 、 S2C S2D 、 | I/O | Multiplexed I/O & Peripheral Pin S2A S2B 、 、 S2C S2D 、 (General) |
| 4 | DA DB 、 、 DC DD 、 | I/O | Multiplexed I/O & Peripheral Pin DA DB 、 、 DC DD 、 (General) |
| 5 | S1A S1B 、 、 S1C S1D 、 | I/O | Multiplexed I/O & Peripheral Pin S1A S1B 、 、 S1C S1D 、 (General) |
| 6 | S2A S2B 、 、 S2C S2D 、 | I/O | Multiplexed I/O & Peripheral Pin S2A S2B 、 、 S2C S2D 、 (General) |
| 7 | DA DB 、 、 DC DD 、 | I/O | Multiplexed I/O & Peripheral Pin DA DB 、 、 DC DD 、 (General) |
| 8 | GND | GND | Ground Reference Pin (GND) |
| 9 | DA DB 、 、 DC DD 、 | I/O | Multiplexed I/O & Peripheral Pin DA DB 、 、 DC DD 、 (General) |
| 10 | S2A S2B 、 、 S2C S2D 、 | I/O | Multiplexed I/O & Peripheral Pin S2A S2B 、 、 S2C S2D 、 (General) |
| 11 | S1A S1B 、 、 S1C S1D 、 | I/O | Multiplexed I/O & Peripheral Pin S1A S1B 、 、 S1C S1D 、 (General) |
| 12 | DA DB 、 、 DC DD 、 | I/O | Multiplexed I/O & Peripheral Pin DA DB 、 、 DC DD 、 (General) |
| 13 | S2A S2B 、 、 S2C S2D 、 | I/O | Multiplexed I/O & Peripheral Pin S2A S2B 、 、 S2C S2D 、 (General) |
| 14 | S1A S1B 、 、 S1C S1D 、 | I/O | Multiplexed I/O & Peripheral Pin S1A S1B 、 、 S1C S1D 、 (General) |
| 15 | EN# | I/O | Multiplexed I/O & Peripheral Pin EN# (General) |
| 16 | VCC | Power | Power Supply Input (VCC — 3.3V / 5.0V Standard Logic) |
| 17 | GND | GND | Ground Reference Pin (GND) |
PIN 1 IN
I/OMultiplexed I/O & Peripheral Pin IN (General)
Design note: 二选 一模拟开关选择输入 ： 高电平选择2#端（S2x） ；低电平选择1#端（S1x）
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 12 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (17 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
QFN-16(3x3) · 3.00×3.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (17 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for CH445 / CH448 / CH440
P13 · p13_fig01EXACT PACKAGE
P13 · p13_fig02EXACT PACKAGE
P2 · p02_fig011491×1615px
P2 · p02_fig01P2
P3 · p03_fig011729×2206px
P9 · p09_fig011725×2761px
P9 · p09_fig01P9
P11 · p11_fig011506×749px
P11 · p11_fig021543×684px
P17 · p17_fig011210×1387px
P14 · p14_fig021341×1017px
P15 · p15_fig011210×1386px
Technical Specifications & Part Details (CH445P)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH445P (QFN-16(3x3)) is a 16-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 1.00 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
550
MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 1.00 mm (A1=0.03 mm)
Package family: QFN (QFN-16(3x3))
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol17 auto-grouped pins
IPC-7351B Land Pattern17 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteEPAD 1.70×1.70mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH445 / CH448 / CH440 (10)
DFN-6(1.2x1.2) · 7P
IPC-7351B
7P1.2×1.2×1.00mmP=0.4mm
CH445 / CH448 / CH440 (DFN-6(1.2x1.2))
MSOP-10 · 10P
MSOP-10 · 10P
SOP-16 · 16P
TSSOP-16 · 16P
TSSOP-16 · 16P
QFN-16(3x3) · 17P
QSOP-24 · 24P
QFN-24-EP(4x4) · 25P
IPC-7351B
25P4.0×4.0×1.00mmP=0.5mm
CH445 / CH448 / CH440 (QFN-24-EP(4x4))
Mechanical Dimensions & Land Pattern (QFN-16(3x3))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.50mm
Pad Size (W × L)Level B
0.29 × 0.77 mm
Pins / Total PadsTopology
17P / 17Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-16(3x3) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH445P (QFN-16(3x3))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH445P (QFN-16(3x3))?
Manufactured by WCH, the CH445P is housed in a QFN-16(3x3) package with 17 pins and a 0.50 mm lead pitch. Key pins include: 1 (IN: Multiplexed I/O & Peripheral Pin IN (General)), 2 (S1A S1B 、 、 S1C S1D 、: Multiplexed I/O & Peripheral Pin S1A S1B 、 、 S1C S1D 、 (General)), 3 (S2A S2B 、 、 S2C S2D 、: Multiplexed I/O & Peripheral Pin S2A S2B 、 、 S2C S2D 、 (General)), 4 (DA DB 、 、 DC DD 、: Multiplexed I/O & Peripheral Pin DA DB 、 、 DC DD 、 (General)), 5 (S1A S1B 、 、 S1C S1D 、: Multiplexed I/O & Peripheral Pin S1A S1B 、 、 S1C S1D 、 (General)), 6 (S2A S2B 、 、 S2C S2D 、: Multiplexed I/O & Peripheral Pin S2A S2B 、 、 S2C S2D 、 (General)).
What are the IPC-7351B PCB Footprint dimensions for CH445P?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH445P (QFN-16(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 17 copper pads plus a central exposed thermal pad (EPAD) of 1.70 × 1.70 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH445P?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH445P (WCH, QFN-16(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (17 pins) & CH445 / CH448 / CH440 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | IN | Digital_IO | Signal terminal IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IN. Supported peripheral buses: General. |
| 2 | S1A S1B 、 、 S1C S1D 、 | Digital_IO | Signal terminal S1A S1B 、 、 S1C S1D 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: S1A S1B 、 、 S1C S1D 、. Supported peripheral buses: General. |
| 3 | S2A S2B 、 、 S2C S2D 、 | Digital_IO | Signal terminal S2A S2B 、 、 S2C S2D 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: S2A S2B 、 、 S2C S2D 、. Supported peripheral buses: General. |
| 4 | DA DB 、 、 DC DD 、 | Digital_IO | Signal terminal DA DB 、 、 DC DD 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DA DB 、 、 DC DD 、. Supported peripheral buses: General. |
| 5 | S1A S1B 、 、 S1C S1D 、 | Digital_IO | Signal terminal S1A S1B 、 、 S1C S1D 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: S1A S1B 、 、 S1C S1D 、. Supported peripheral buses: General. |
| 6 | S2A S2B 、 、 S2C S2D 、 | Digital_IO | Signal terminal S2A S2B 、 、 S2C S2D 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: S2A S2B 、 、 S2C S2D 、. Supported peripheral buses: General. |
| 7 | DA DB 、 、 DC DD 、 | Digital_IO | Signal terminal DA DB 、 、 DC DD 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DA DB 、 、 DC DD 、. Supported peripheral buses: General. |
| 8 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 9 | DA DB 、 、 DC DD 、 | Digital_IO | Signal terminal DA DB 、 、 DC DD 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DA DB 、 、 DC DD 、. Supported peripheral buses: General. |
| 10 | S2A S2B 、 、 S2C S2D 、 | Digital_IO | Signal terminal S2A S2B 、 、 S2C S2D 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: S2A S2B 、 、 S2C S2D 、. Supported peripheral buses: General. |
| 11 | S1A S1B 、 、 S1C S1D 、 | Digital_IO | Signal terminal S1A S1B 、 、 S1C S1D 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: S1A S1B 、 、 S1C S1D 、. Supported peripheral buses: General. |
| 12 | DA DB 、 、 DC DD 、 | Digital_IO | Signal terminal DA DB 、 、 DC DD 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DA DB 、 、 DC DD 、. Supported peripheral buses: General. |
| 13 | S2A S2B 、 、 S2C S2D 、 | Digital_IO | Signal terminal S2A S2B 、 、 S2C S2D 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: S2A S2B 、 、 S2C S2D 、. Supported peripheral buses: General. |
| 14 | S1A S1B 、 、 S1C S1D 、 | Digital_IO | Signal terminal S1A S1B 、 、 S1C S1D 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: S1A S1B 、 、 S1C S1D 、. Supported peripheral buses: General. |
| 15 | EN# | Digital_IO | Signal terminal EN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: EN#. Supported peripheral buses: General. |
| 16 | VCC | Power_In | Primary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 17 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |