STM32H503EBY6TR (WLCSP-25(2.2x2.3)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of STM32H503EBY6TR (WLCSP-25(2.2x2.3))?

Manufactured by ST, the STM32H503EBY6TR is housed in a WLCSP-25(2.2x2.3) package with 25 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (PA12: Multiplexed I/O & Peripheral Pin PA12 (General)), A2 (PA15: Multiplexed I/O & Peripheral Pin PA15 (General)), A3 (BOOT0: Input-Only Pin BOOT0 (General)), A4 (PB7: Multiplexed I/O & Peripheral Pin PB7 (General)), A5 (PB8: Multiplexed I/O & Peripheral Pin PB8 (General)), B1 (PA11: Multiplexed I/O & Peripheral Pin PA11 (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for STM32H503EBY6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H503EBY6TR (WLCSP-25(2.2x2.3)) has a nominal body envelope of 2.30 × 2.20 mm, pitch e = 0.40 mm, and 25 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H503EBY6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H503EBY6TR (ST, WLCSP-25(2.2x2.3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 2.30mm × 2.20mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (25/25)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
A1	PA12	I/O	Multiplexed I/O & Peripheral Pin PA12 (General)
A2	PA15	I/O	Multiplexed I/O & Peripheral Pin PA15 (General)
A3	BOOT0	I	Input-Only Pin BOOT0 (General)
A4	PB7	I/O	Multiplexed I/O & Peripheral Pin PB7 (General)
A5	PB8	I/O	Multiplexed I/O & Peripheral Pin PB8 (General)
B1	PA11	I/O	Multiplexed I/O & Peripheral Pin PA11 (General)
B2	VDDIO2	Power	Power Supply Input (VDDIO2 — 3.3V VDD (Max 4.0V))
B3	PB5	I/O	Multiplexed I/O & Peripheral Pin PB5 (General)
B4	PB6	I/O	Multiplexed I/O & Peripheral Pin PB6 (General)
B5	IOB5	I/O	General Purpose Digital I/O Pin IOB5
C1	PA8	I/O	Multiplexed I/O & Peripheral Pin PA8 (General)
C2	PA14	I/O	Multiplexed I/O & Peripheral Pin PA14 (General)
C3	VSSA	GND	Ground Reference Pin (VSSA)
C4	PB4	I/O	Multiplexed I/O & Peripheral Pin PB4 (General)
C5	IOC5	I/O	General Purpose Digital I/O Pin IOC5
D1	PA9	I/O	Multiplexed I/O & Peripheral Pin PA9 (General)
D2	PA13	I/O	Multiplexed I/O & Peripheral Pin PA13 (General)
D3	PB3	I/O	Multiplexed I/O & Peripheral Pin PB3 (General)
D4	VDDA	Power	Power Supply Input (VDDA — 3.3V VDD (Max 4.0V))
D5	NRST	I	System Enable & Hardware Reset (NRST)
E1	PB15	I/O	Multiplexed I/O & Peripheral Pin PB15 (General)
E2	VCAP	I/O	Multiplexed I/O & Peripheral Pin VCAP (General)
E3	PA7	I/O	Multiplexed I/O & Peripheral Pin PA7 (General)
E4	PA5	I/O	Multiplexed I/O & Peripheral Pin PA5 (General)
E5	PA0	I/O	Multiplexed I/O & Peripheral Pin PA0 (UART, SPI, PWM, RTC/CLK)

PIN A1 PA12

I/O

Multiplexed I/O & Peripheral Pin PA12 (General)

Design note: Signal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 23 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

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PDF VIEWEROfficial Datasheet Document: STM32H503EBY6TR (ST · WLCSP-25(2.2x2.3))

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1. Realistic 3D PackageREPRESENTATIVE

STM32H503EBY6TR (WLCSP-25(2.2x2.3)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

STM32H503EBY6TR (WLCSP-25(2.2x2.3)) - 2. Standard Pinout (Top View)

True package pinout (25 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

STM32H503EBY6TR (WLCSP-25(2.2x2.3)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

STM32H503EBY6TR (WLCSP-25(2.2x2.3)) - 4. Package Dimensions (D×E×A)

WLCSP-25(2.2x2.3) · 2.30×2.20mm · Pitch 0.40mmExpand ›

5. Recommended Land PatternLAND PATTERN

STM32H503EBY6TR (WLCSP-25(2.2x2.3)) - 5. Recommended Land Pattern

IPC-7351B Footprint (25 Pads)Expand ›

6. Application SchematicSCHEMATIC

STM32H503EBY6TR (WLCSP-25(2.2x2.3)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (23 figures · Page 1/2)

Showing 1–12 of 23 uncropped original figures for STM32H503

P48 · p48_fig01EXACT PACKAGE

Figure 4. WLCSP25 pinout 1 2 3 4 5

P155 · p155_fig01EXACT PACKAGE

Figure 35. WLCSP25 - Outline

P1 · p01_fig011751×736px

• VBAT supply for RTC, 32 backup registers (32 bits)

P48 · p48_fig021559×1093px

Figure 5. UFQFPN32 pinout(a)

P48 · p48_fig01P48

Datasheet Page 48 (p48_fig01)

P49 · p49_fig011546×999px

Figure 6. LQFP48 pinout

P49 · p49_fig021559×1306px

STM32H503EBY6TR (WLCSP-25(2.2x2.3)) — 10

P50 · p50_fig011546×1101px

Figure 8. LQFP64 pinout VCAP 61 1 3 4

P71 · p71_fig011550×1985px

Figure 11. Power supply scheme

P71 · p71_fig01P71

Datasheet Page 71 (p71_fig01)

P98 · p98_fig011546×702px

Figure 16. Typical application with an 8 MHz crystal

P99 · p99_fig011546×704px

Figure 17. Typical application with a 32.768 kHz crystal

Page 1 / 2 (23 extracted figures)

Technical Specifications & Part Details (STM32H503EBY6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Embedded Microcontroller Unit (MCU)

Detailed Overview:STM32H503EBY6TR (WLCSP-25(2.2x2.3)) is a 25-pin embedded microcontroller unit (mcu) featuring a 2.20 × 2.30 × 0.55 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

1.71 V to 3.6 V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

250 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

3 5V-tolerant (FT) pins detected

Package Envelope (D × E × A)D × E × A

2.20 × 2.30 × 0.55 mm (A1=0.17 mm)

Package family: WLCSP (WLCSP-25(2.2x2.3))

Pin Count & Lead PitchN / e

25 Pins | Pitch e = 0.40 mm (15.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

USB, UART, SPI, I2C, I2S, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol25 auto-grouped pins

IPC-7351B Land Pattern25 pads · Pitch 0.40mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

IPC-7351B

Family Variants & Same Datasheet Chips — STM32H503 (7)

Select package variant or sibling MPN sharing this datasheet

WLCSP-25(2.2x2.3) · 25P

STM32H503EBY6TR

ST·WLCSP-25(2.2x2.3)

IPC-7351B

25P2.2×2.3×0.55mmP=0.4mm

STM32H503 (WLCSP-25(2.2x2.3))

LQFP-48(7x7) · 48P

STM32H503CBT6

ST·LQFP-48(7x7)

IPC-7351B

48P7.0×7.0×1.60mmP=0.5mm

STM32H503 (LQFP-48(7x7))

LQFP-48(7x7) · 48P

STM32H503CBT7

ST·LQFP-48(7x7)

IPC-7351B

48P7.0×7.0×1.60mmP=0.5mm

STM32H503 (LQFP-48(7x7))

UFQFPN-48(7x7) · 49P

STM32H503CBU7

ST·UFQFPN-48(7x7)

IPC-7351B

49P7.0×7.0×0.55mmP=0.5mm

STM32H503 (UFQFPN-48(7x7))

UFQFPN-48-EP(7x7) · 49P

STM32H503CBU6

ST·UFQFPN-48-EP(7x7)

IPC-7351B

49P7.0×7.0×0.55mmP=0.5mm

STM32H503 (UFQFPN-48-EP(7x7))

LQFP-64(10x10) · 64P

STM32H503RBT6

ST·LQFP-64(10x10)

IPC-7351B

64P10.0×10.0×1.60mmP=0.5mm

STM32H503 (LQFP-64(10x10))

LQFP-64(10x10) · 64P

STM32H503RBT7

ST·LQFP-64(10x10)

IPC-7351B

64P10.0×10.0×1.60mmP=0.5mm

STM32H503 (LQFP-64(10x10))

Mechanical Dimensions & Land Pattern (WLCSP-25(2.2x2.3))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

2.20 × 2.30 mm

Height (A) & Pitch (e)IPC-7351B

A=0.55mm · e=0.40mm

Pad Size (W × L)Level B

0.21 × 0.21 mm

Pins / Total PadsTopology

25P / 25Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit WLCSP-25(2.2x2.3)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32H503EBY6TR (WLCSP-25(2.2x2.3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32H503EBY6TR (WLCSP-25(2.2x2.3))?

Manufactured by ST, the STM32H503EBY6TR is housed in a WLCSP-25(2.2x2.3) package with 25 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (PA12: Multiplexed I/O & Peripheral Pin PA12 (General)), A2 (PA15: Multiplexed I/O & Peripheral Pin PA15 (General)), A3 (BOOT0: Input-Only Pin BOOT0 (General)), A4 (PB7: Multiplexed I/O & Peripheral Pin PB7 (General)), A5 (PB8: Multiplexed I/O & Peripheral Pin PB8 (General)), B1 (PA11: Multiplexed I/O & Peripheral Pin PA11 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32H503EBY6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H503EBY6TR (WLCSP-25(2.2x2.3)) has a nominal body envelope of 2.30 × 2.20 mm, pitch e = 0.40 mm, and 25 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H503EBY6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H503EBY6TR (ST, WLCSP-25(2.2x2.3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (25 pins) & STM32H503 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
A1	PA12	Digital_IO	Signal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
A2	PA15	Digital_IO	Signal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
A3	BOOT0	Digital_IO	Signal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
A4	PB7	Digital_IO	Signal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
A5	PB8	Digital_IO	Signal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
B1	PA11	Digital_IO	Signal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
B2	VDDIO2	Power_In	Primary positive power supply input (VDDIO2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B3	PB5	Digital_IO	Signal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
B4	PB6	Digital_IO	Signal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
B5	IOB5	Digital_IO	General Purpose Digital I/O Pin IOB5
C1	PA8	Digital_IO	Signal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
C2	PA14	Digital_IO	Signal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
C3	VSSA	GND	0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
C4	PB4	Digital_IO	Signal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
C5	IOC5	Digital_IO	General Purpose Digital I/O Pin IOC5
D1	PA9	Digital_IO	Signal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
D2	PA13	Digital_IO	Signal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
D3	PB3	Digital_IO	Signal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
D4	VDDA	Power_In	Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D5	NRST	Digital_IO	Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
E1	PB15	Digital_IO	Signal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
E2	VCAP	Digital_IO	Signal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
E3	PA7	Digital_IO	Signal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
E4	PA5	Digital_IO	Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
E5	PA0	Digital_IO	Signal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_RDY, SPI3_NSS, SPI1_MISO. Supported peripheral buses: UART, SPI, PWM, RTC/CLK.

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