Mechanical Dimensions & Land Pattern (QFN-24(4x4))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
25P / 25Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-24(4x4) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — SM802124UMG-TR (QFN-24(4x4))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of SM802124UMG-TR (QFN-24(4x4))?
Manufactured by MICROCHIP, the SM802124UMG-TR is housed in a QFN-24(4x4) package with 25 pins and a 0.50 mm lead pitch. Key pins include: 1 (VDDO: Regulated Power Output (VDDO — 3.3V / 5.0V Standard Logic)), 2 (VSSO: Ground Reference Pin (VSSO)), 3 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 4 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 5 (PLL_BYPASS: Multiplexed I/O & Peripheral Pin PLL_BYPASS (General)), 6 (VSS: Ground Reference Pin (VSS)).
What are the IPC-7351B PCB Footprint dimensions for SM802124UMG-TR?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), SM802124UMG-TR (QFN-24(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 25 copper pads plus a central exposed thermal pad (EPAD) of 2.70 × 2.70 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for SM802124UMG-TR?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for SM802124UMG-TR (MICROCHIP, QFN-24(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (25 pins) & SM80212 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | VDDO | Power_Out | Regulated power output rail (VDDO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 2 | VSSO | GND | 0V electrical ground return terminal (VSSO) for internal core logic, I/O drivers, and analog sub-blocks. |
| 3 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 4 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 5 | PLL_BYPASS | Digital_IO | Signal terminal PLL_BYPASS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PLL_BYPASS. Supported peripheral buses: General. |
| 6 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 7 | TEST | Digital_IO | Signal terminal TEST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TEST. Supported peripheral buses: General. |
| 8 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 9 | REF_IN | Digital_IO | Signal terminal REF_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: REF_IN. Supported peripheral buses: General. |
| 10 | TEST | Digital_IO | Signal terminal TEST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TEST. Supported peripheral buses: General. |
| 11 | TEST | Digital_IO | Signal terminal TEST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TEST. Supported peripheral buses: General. |
| 12 | TEST | Digital_IO | Signal terminal TEST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TEST. Supported peripheral buses: General. |
| 13 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 14 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 15 | TEST | Digital_IO | Signal terminal TEST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TEST. Supported peripheral buses: General. |
| 16 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 17 | Q0 | Digital_IO | Signal terminal Q0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Q0. Supported peripheral buses: General. |
| 18 | VDDO | Power_Out | Regulated power output rail (VDDO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 19 | TEST | Digital_IO | Signal terminal TEST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TEST. Supported peripheral buses: General. |
| 20 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 21 | Q1 | Digital_IO | Signal terminal Q1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Q1. Supported peripheral buses: General. |
| 22 | VSSO | GND | 0V electrical ground return terminal (VSSO) for internal core logic, I/O drivers, and analog sub-blocks. |
| 23 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 24 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 25 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |