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CAP1208-1-A4-TR (QFN-16-EP(3x3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CAP1208-1-A4-TR

MICROCHIPID: C2652055QFN-16-EP(3x3) · 17 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CAP1208-1-A4-TR (QFN-16-EP(3x3))1ALERT#2SMDATA3SMCLK4VDD5N/C6N/C7GND8GND9CS817EP16CS115CS214CS313CS412CS511CS610CS7Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617E=3.00mm · Pitch e=0.50mmD=3.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.00mm × 3.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (17/17)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1ALERT#I/OMultiplexed I/O & Peripheral Pin ALERT# (General)
2SMDATAI/OMultiplexed I/O & Peripheral Pin SMDATA (General)
3SMCLKI/OMultiplexed I/O & Peripheral Pin SMCLK (General)
4VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
5N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
6N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
7GNDGNDGround Reference Pin (GND)
8GNDGNDGround Reference Pin (GND)
9CS8I/OMultiplexed I/O & Peripheral Pin CS8 (General)
10CS7I/OMultiplexed I/O & Peripheral Pin CS7 (General)
11CS6I/OMultiplexed I/O & Peripheral Pin CS6 (General)
12CS5I/OMultiplexed I/O & Peripheral Pin CS5 (General)
13CS4I/OMultiplexed I/O & Peripheral Pin CS4 (General)
14CS3I/OMultiplexed I/O & Peripheral Pin CS3 (General)
15CS2I/OMultiplexed I/O & Peripheral Pin CS2 (General)
16CS1I/OMultiplexed I/O & Peripheral Pin CS1 (General)
17EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 ALERT#
I/O
Multiplexed I/O & Peripheral Pin ALERT# (General)
Design note: Signal terminal ALERT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ALERT#. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CAP1208-1-A4-TR (MICROCHIP · QFN-16-EP(3x3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CAP1208-1-A4-TR (QFN-16-EP(3x3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CAP1208-1-A4-TR (QFN-16-EP(3x3)) - 2. Standard Pinout (Top View)
True package pinout (17 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CAP1208-1-A4-TR (QFN-16-EP(3x3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CAP1208-1-A4-TR (QFN-16-EP(3x3)) - 4. Package Dimensions (D×E×A)
QFN-16-EP(3x3) · 3.00×3.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CAP1208-1-A4-TR (QFN-16-EP(3x3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (17 Pads)Expand ›
6. Application SchematicSCHEMATIC
CAP1208-1-A4-TR (QFN-16-EP(3x3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CAP1208
P1 · p01_fig01377×200px
CAP1208-1-A4-TR (QFN-16-EP(3x3)) — 8-Channel Capacitive Touch Sensor
8-Channel Capacitive Touch Sensor
P5 · p05_fig01786×715px
CAP1208-1-A4-TR (QFN-16-EP(3x3)) — FIGURE 1-3: CAP1208 PIN DIAGRAM (16-PIN QFN)
FIGURE 1-3: CAP1208 PIN DIAGRAM (16-PIN QFN)
P5 · p05_fig01P5
CAP1208-1-A4-TR (QFN-16-EP(3x3)) — Datasheet Page 5 (p05_fig01)
Datasheet Page 5 (p05_fig01)
P54 · p54_fig011279×1076px
CAP1208-1-A4-TR (QFN-16-EP(3x3)) — FIGURE 6-3: CAP1208 PACKAGE DIMENSIONS - 16-PIN QFN 3MM X 3MM
FIGURE 6-3: CAP1208 PACKAGE DIMENSIONS - 16-PIN QFN 3MM X 3MM
P54 · p54_fig01P54
CAP1208-1-A4-TR (QFN-16-EP(3x3)) — Datasheet Page 54 (p54_fig01)
Datasheet Page 54 (p54_fig01)
P55 · p55_fig011642×1254px
CAP1208-1-A4-TR (QFN-16-EP(3x3)) — FIGURE 6-4: CAP1208 PCB LAND PATTERN AND STENCIL - 16-PIN QFN 3MM X 3MM
FIGURE 6-4: CAP1208 PCB LAND PATTERN AND STENCIL - 16-PIN QFN 3MM X 3MM
P55 · p55_fig01P55
CAP1208-1-A4-TR (QFN-16-EP(3x3)) — Datasheet Page 55 (p55_fig01)
Datasheet Page 55 (p55_fig01)
P50 · p50_fig01All Packages in PDF
CAP1208-1-A4-TR (QFN-16-EP(3x3)) — FIGURE 6-1: CAP1208 14-LEAD PLASTIC SMALL OUTLINE, NARROW, 3.90 MM BODY (SOIC)
FIGURE 6-1: CAP1208 14-LEAD PLASTIC SMALL OUTLINE, NARROW, 3.90 MM BODY (SOIC)
P51 · p51_fig01All Packages in PDF
CAP1208-1-A4-TR (QFN-16-EP(3x3)) — FIGURE 6-1: CAP1208 14-LEAD PLASTIC SMALL OUTLINE, NARROW, 3.90 MM BODY (SOIC)
FIGURE 6-1: CAP1208 14-LEAD PLASTIC SMALL OUTLINE, NARROW, 3.90 MM BODY (SOIC)

Technical Specifications & Part Details (CAP1208-1-A4-TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CAP1208-1-A4-TR (QFN-16-EP(3x3)) is a 16-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated I2C interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-16-EP(3x3))
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol17 auto-grouped pins
OK
IPC-7351B Land Pattern17 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 1.50×1.50mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-16-EP(3x3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
17P / 17Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-16-EP(3x3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CAP1208-1-A4-TR (QFN-16-EP(3x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CAP1208-1-A4-TR (QFN-16-EP(3x3))?

Manufactured by MICROCHIP, the CAP1208-1-A4-TR is housed in a QFN-16-EP(3x3) package with 17 pins and a 0.50 mm lead pitch. Key pins include: 1 (ALERT#: Multiplexed I/O & Peripheral Pin ALERT# (General)), 2 (SMDATA: Multiplexed I/O & Peripheral Pin SMDATA (General)), 3 (SMCLK: Multiplexed I/O & Peripheral Pin SMCLK (General)), 4 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), 5 (N/C: Multiplexed I/O & Peripheral Pin N/C (General)), 6 (N/C: Multiplexed I/O & Peripheral Pin N/C (General)).

What are the IPC-7351B PCB Footprint dimensions for CAP1208-1-A4-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CAP1208-1-A4-TR (QFN-16-EP(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 17 copper pads plus a central exposed thermal pad (EPAD) of 1.50 × 1.50 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CAP1208-1-A4-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CAP1208-1-A4-TR (MICROCHIP, QFN-16-EP(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (17 pins) & CAP1208 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1ALERT#Digital_IOSignal terminal ALERT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ALERT#. Supported peripheral buses: General.
2SMDATADigital_IOSignal terminal SMDATA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SMDATA. Supported peripheral buses: General.
3SMCLKDigital_IOSignal terminal SMCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SMCLK. Supported peripheral buses: General.
4VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
5N/CDigital_IOSignal terminal N/C (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
6N/CDigital_IOSignal terminal N/C (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
7GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
8GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
9CS8Digital_IOSignal terminal CS8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS8. Supported peripheral buses: General.
10CS7Digital_IOSignal terminal CS7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS7. Supported peripheral buses: General.
11CS6Digital_IOSignal terminal CS6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS6. Supported peripheral buses: General.
12CS5Digital_IOSignal terminal CS5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS5. Supported peripheral buses: General.
13CS4Digital_IOSignal terminal CS4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS4. Supported peripheral buses: General.
14CS3Digital_IOSignal terminal CS3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS3. Supported peripheral buses: General.
15CS2Digital_IOSignal terminal CS2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS2. Supported peripheral buses: General.
16CS1Digital_IOSignal terminal CS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS1. Supported peripheral buses: General.
17EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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