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PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC16LF18326-E/JQ

MICROCHIPID: C220686TQFN-16-EP(4x4) · 17 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC16LF18326-E/JQ (TQFN-16-EP(4x4))1RA52RA43RA3/#MCLR/VP4RC55RC46RC37RC28RC19RC017EP16VDD15NC14NC13VSS12RA0/ICSPDAT11RA1/ICSPCLK10RA2Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617E=4.00mm · Pitch e=0.65mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (17/17)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RA5I/OMultiplexed I/O & Peripheral Pin RA5 (General)
2RA4I/OMultiplexed I/O & Peripheral Pin RA4 (General)
3RA3/#MCLR/VPPI/OMultiplexed I/O & Peripheral Pin RA3/#MCLR/VPP (General)
4RC5I/OMultiplexed I/O & Peripheral Pin RC5 (General)
5RC4I/OMultiplexed I/O & Peripheral Pin RC4 (General)
6RC3I/OMultiplexed I/O & Peripheral Pin RC3 (General)
7RC2I/OMultiplexed I/O & Peripheral Pin RC2 (General)
8RC1I/OMultiplexed I/O & Peripheral Pin RC1 (General)
9RC0I/OMultiplexed I/O & Peripheral Pin RC0 (General)
10RA2I/OMultiplexed I/O & Peripheral Pin RA2 (General)
11RA1/ICSPCLKI/OMultiplexed I/O & Peripheral Pin RA1/ICSPCLK (General)
12RA0/ICSPDATI/OMultiplexed I/O & Peripheral Pin RA0/ICSPDAT (General)
13VSSGNDGround Reference Pin (VSS)
14NCI/OMultiplexed I/O & Peripheral Pin NC (General)
15NCI/OMultiplexed I/O & Peripheral Pin NC (General)
16VDDPowerPower Supply Input (VDD — 1.8V to 3.6V)
17EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 RA5
I/O
Multiplexed I/O & Peripheral Pin RA5 (General)
Design note: Signal terminal RA5 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA5. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC16LF18326-E/JQ (MICROCHIP · TQFN-16-EP(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) - 2. Standard Pinout (Top View)
True package pinout (17 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) - 4. Package Dimensions (D×E×A)
TQFN-16-EP(4x4) · 4.00×4.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (17 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for PIC16LF18326
P1 · p01_fig01376×200px
PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) — Full-Featured, 14/20 Low Pin Count Microcontrollers with XLP
Full-Featured, 14/20 Low Pin Count Microcontrollers with XLP
P22 · p22_fig011777×1102px
PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) — FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS (Note 1) VDD R1
FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS (Note 1) VDD R1
P304 · p304_fig011695×506px
PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) — FIGURE 29-2: COMPARE MODE OPERATION BLOCK DIAGRAM
FIGURE 29-2: COMPARE MODE OPERATION BLOCK DIAGRAM
P304 · p304_fig021627×697px
PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) — FIGURE 29-2: COMPARE MODE OPERATION BLOCK DIAGRAM
FIGURE 29-2: COMPARE MODE OPERATION BLOCK DIAGRAM
P323 · p323_fig01867×566px
PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) — FIGURE 30-11: I2C MASTER/ SLAVE CONNECTION
FIGURE 30-11: I2C MASTER/ SLAVE CONNECTION
P395 · p395_fig021254×1015px
PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) — FIGURE 33-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
FIGURE 33-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
P395 · p395_fig02P395
PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) — Datasheet Page 395 (p395_fig02)
Datasheet Page 395 (p395_fig02)
P396 · p396_fig01870×1368px
PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) — The literal and control category contains the most varied instruction word format.
The literal and control category contains the most varied instruction word format.
P456 · p456_fig011777×2500px
PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) — DS40001839B-page 456 Preliminary  2016-2017 Microchip Technology Inc. | Microchip Technology Drawing C04-257A Sheet 2 of 2 | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.micr
DS40001839B-page 456 Preliminary  2016-2017 Microchip Technology Inc. | Microchip Technology Drawing C04-257A Sheet 2 of 2 | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.micr
P456 · p456_fig01P456
PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) — Datasheet Page 456 (p456_fig01)
Datasheet Page 456 (p456_fig01)
P457 · p457_fig011777×2500px
PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) —  2016-2017 Microchip Technology Inc. Preliminary DS40001839B-page 457 | RECOMMENDED LAND PATTERN | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note:
 2016-2017 Microchip Technology Inc. Preliminary DS40001839B-page 457 | RECOMMENDED LAND PATTERN | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note:
P457 · p457_fig01P457
PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) — Datasheet Page 457 (p457_fig01)
Datasheet Page 457 (p457_fig01)
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (PIC16LF18326-E/JQ)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) is a 16-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.90 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V to 3.6V supply operation across -40°C to 85°C with integrated UART, SPI, I2C, ADC, DAC, PWM interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V to 3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (TQFN-16-EP(4x4))
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, DAC, PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol17 auto-grouped pins
OK
IPC-7351B Land Pattern17 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteEPAD 2.10×2.10mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TQFN-16-EP(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.65mm
Pad Size (W × L)Level B
0.36 × 1.09 mm
Pins / Total PadsTopology
17P / 17Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TQFN-16-EP(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC16LF18326-E/JQ (TQFN-16-EP(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC16LF18326-E/JQ (TQFN-16-EP(4x4))?

Manufactured by MICROCHIP, the PIC16LF18326-E/JQ is housed in a TQFN-16-EP(4x4) package with 17 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 1.8V to 3.6V. Key pins include: 1 (RA5: Multiplexed I/O & Peripheral Pin RA5 (General)), 2 (RA4: Multiplexed I/O & Peripheral Pin RA4 (General)), 3 (RA3/#MCLR/VPP: Multiplexed I/O & Peripheral Pin RA3/#MCLR/VPP (General)), 4 (RC5: Multiplexed I/O & Peripheral Pin RC5 (General)), 5 (RC4: Multiplexed I/O & Peripheral Pin RC4 (General)), 6 (RC3: Multiplexed I/O & Peripheral Pin RC3 (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC16LF18326-E/JQ?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16LF18326-E/JQ (TQFN-16-EP(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.65 mm, and 17 copper pads plus a central exposed thermal pad (EPAD) of 2.10 × 2.10 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16LF18326-E/JQ?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16LF18326-E/JQ (MICROCHIP, TQFN-16-EP(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (17 pins) & PIC16LF18326 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RA5Digital_IOSignal terminal RA5 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA5. Supported peripheral buses: General.
2RA4Digital_IOSignal terminal RA4 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA4. Supported peripheral buses: General.
3RA3/#MCLR/VPPDigital_IOSignal terminal RA3/#MCLR/VPP (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA3/#MCLR/VPP. Supported peripheral buses: General.
4RC5Digital_IOSignal terminal RC5 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC5. Supported peripheral buses: General.
5RC4Digital_IOSignal terminal RC4 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC4. Supported peripheral buses: General.
6RC3Digital_IOSignal terminal RC3 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC3. Supported peripheral buses: General.
7RC2Digital_IOSignal terminal RC2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC2. Supported peripheral buses: General.
8RC1Digital_IOSignal terminal RC1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC1. Supported peripheral buses: General.
9RC0Digital_IOSignal terminal RC0 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC0. Supported peripheral buses: General.
10RA2Digital_IOSignal terminal RA2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA2. Supported peripheral buses: General.
11RA1/ICSPCLKDigital_IOSignal terminal RA1/ICSPCLK (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA1/ICSPCLK. Supported peripheral buses: General.
12RA0/ICSPDATDigital_IOSignal terminal RA0/ICSPDAT (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA0/ICSPDAT. Supported peripheral buses: General.
13VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
14NCNCSignal terminal NC (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
15NCNCSignal terminal NC (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
16VDDPower_InPrimary positive power supply input (VDD) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
17EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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