PIC32MX170F256B-I/ML (QFN-28-EP(6x6)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of PIC32MX170F256B-I/ML (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the PIC32MX170F256B-I/ML is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.3V to 3.6V. Key pins include: 1 (PGED1: Multiplexed I/O & Peripheral Pin PGED1 (General)), 2 (PGEC1: Multiplexed I/O & Peripheral Pin PGEC1 (General)), 3 (CTED13: Multiplexed I/O & Peripheral Pin CTED13 (General)), 4 (C2INC: Multiplexed I/O & Peripheral Pin C2INC (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (RA2: Multiplexed I/O & Peripheral Pin RA2 (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for PIC32MX170F256B-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC32MX170F256B-I/ML (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC32MX170F256B-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC32MX170F256B-I/ML (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 6.00mm × 6.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	PGED1	I/O	Multiplexed I/O & Peripheral Pin PGED1 (General)
2	PGEC1	I/O	Multiplexed I/O & Peripheral Pin PGEC1 (General)
3	CTED13	I/O	Multiplexed I/O & Peripheral Pin CTED13 (General)
4	C2INC	I/O	Multiplexed I/O & Peripheral Pin C2INC (General)
5	VSS	GND	Ground Reference Pin (VSS)
6	RA2	I/O	Multiplexed I/O & Peripheral Pin RA2 (General)
7	RA3	I/O	Multiplexed I/O & Peripheral Pin RA3 (General)
8	PMA0	I/O	Multiplexed I/O & Peripheral Pin PMA0 (General)
9	CTED9	I/O	Multiplexed I/O & Peripheral Pin CTED9 (General)
10	VDD	Power	Power Supply Input (VDD — 2.3V to 3.6V)
11	RB5	I/O	Multiplexed I/O & Peripheral Pin RB5 (General)
12	PGEC3/RPB6/PMD6/RB6	I/O	Multiplexed I/O & Peripheral Pin PGEC3/RPB6/PMD6/RB6 (General)
13	CTED3	I/O	Multiplexed I/O & Peripheral Pin CTED3 (General)
14	CTED10	I/O	Multiplexed I/O & Peripheral Pin CTED10 (General)
15	CTED4	I/O	Multiplexed I/O & Peripheral Pin CTED4 (General)
16	VSS	GND	Ground Reference Pin (VSS)
17	VCAP	I/O	Multiplexed I/O & Peripheral Pin VCAP (General)
18	PGED2	I/O	Multiplexed I/O & Peripheral Pin PGED2 (General)
19	PGEC2	I/O	Multiplexed I/O & Peripheral Pin PGEC2 (General)
20	AN12/PMD0/RB12	I/O	Multiplexed I/O & Peripheral Pin AN12/PMD0/RB12 (General)
21	CTPLS	I/O	Multiplexed I/O & Peripheral Pin CTPLS (General)
22	CTED5	I/O	Multiplexed I/O & Peripheral Pin CTED5 (General)
23	CTED6	I/O	Multiplexed I/O & Peripheral Pin CTED6 (General)
24	AVSS	GND	Ground Reference Pin (AVSS)
25	AVDD	Power	Power Supply Input (AVDD — 2.3V to 3.6V)
26	MCLR	I/O	Multiplexed I/O & Peripheral Pin MCLR (General)
27	VREF+	Analog	Multiplexed I/O & Peripheral Pin VREF+ (General)
28	VREF-	Analog	Multiplexed I/O & Peripheral Pin VREF- (General)
29	PMCS1	I/O	Multiplexed I/O & Peripheral Pin PMCS1 (General)

PIN 1 PGED1

I/O

Multiplexed I/O & Peripheral Pin PGED1 (General)

Design note: DataI/OpinforProgramming/Debugging CommunicationChannel1

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

PIC32MX170F256B-I/ML (QFN-28-EP(6x6)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

PIC32MX170F256B-I/ML (QFN-28-EP(6x6)) - 2. Standard Pinout (Top View)

True package pinout (29 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

PIC32MX170F256B-I/ML (QFN-28-EP(6x6)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

PIC32MX170F256B-I/ML (QFN-28-EP(6x6)) - 4. Package Dimensions (D×E×A)

QFN-28-EP(6x6) · 6.00×6.00mm · Pitch 0.65mmExpand ›

5. Recommended Land PatternLAND PATTERN

PIC32MX170F256B-I/ML (QFN-28-EP(6x6)) - 5. Recommended Land Pattern

IPC-7351B Footprint (29 Pads)Expand ›

6. Application SchematicSCHEMATIC

PIC32MX170F256B-I/ML (QFN-28-EP(6x6)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)

Showing 1–12 of 12 uncropped original figures for PIC32MX250F1 / PIC32MX170F2

P1 · p01_fig01377×200px

PIC32MX170F256B-I/ML (QFN-28-EP(6x6)) — 32-bit Microcontrollers (up to 256 KB Flash and 64 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

32-bit Microcontrollers (up to 256 KB Flash and 64 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

P19 · p19_fig011548×1545px

FIGURE 1-1: BLOCK DIAGRAM

P31 · p31_fig011730×1260px

FIGURE 2-5: CAPACITIVE TOUCH SENSING WITH GRAPHICS APPLICATION

P31 · p31_fig021549×666px

FIGURE 2-6: AUDIO PLAYBACK APPLICATION

P31 · p31_fig01P31

Datasheet Page 31 (p31_fig01)

P32 · p32_fig011446×720px

FIGURE 2-7: REMOTE CIRCUIT WITH AN INDEPENDENT POWER SOURCE

P33 · p33_fig011684×740px

FIGURE 2-8: DIGITAL AND ANALOG SIGNAL ISOLATION

P131 · p131_fig01867×929px

FIGURE 11-2: REMAPPABLE INPUT EXAMPLE FOR U1RX

P191 · p191_fig011587×671px

Figure 20-1 illustrates the PMP module block diagram.

P191 · p191_fig021195×1043px

FIGURE 20-1: PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES

P191 · p191_fig02P191

Datasheet Page 191 (p191_fig02)

P313 · p313_fig011778×2571px

PIC32MX1XX/2XX 28/36/44-PIN FAMILY

Technical Specifications & Part Details (PIC32MX170F256B-I/ML)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:PIC32MX170F256B-I/ML (QFN-28-EP(6x6)) is a 28-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 2.3V to 3.6V supply operation across -40°C to +85°C with integrated USB, UART, SPI, I2C, I2S, ADC, JTAG / SWD, IrDA interfaces.

Operating Supply VoltageV_CC / V_DD

2.3V to 3.6V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to +85°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

40 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

6.00 × 6.00 × 1.00 mm (A1=0.03 mm)

Package family: QFN (QFN-28-EP(6x6))

Pin Count & Lead PitchN / e

28 Pins | Pitch e = 0.65 mm (25.6 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

USB, UART, SPI, I2C, I2S, ADC, JTAG / SWD, IrDA

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol29 auto-grouped pins

IPC-7351B Land Pattern29 pads · Pitch 0.65mm

IPC-7525 60% Solder PasteEPAD 4.70×4.70mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-28-EP(6x6))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

6.00 × 6.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.00mm · e=0.65mm

Pad Size (W × L)Level B

0.28 × 0.80 mm

Pins / Total PadsTopology

29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit QFN-28-EP(6x6)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC32MX170F256B-I/ML (QFN-28-EP(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC32MX170F256B-I/ML (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the PIC32MX170F256B-I/ML is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.3V to 3.6V. Key pins include: 1 (PGED1: Multiplexed I/O & Peripheral Pin PGED1 (General)), 2 (PGEC1: Multiplexed I/O & Peripheral Pin PGEC1 (General)), 3 (CTED13: Multiplexed I/O & Peripheral Pin CTED13 (General)), 4 (C2INC: Multiplexed I/O & Peripheral Pin C2INC (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (RA2: Multiplexed I/O & Peripheral Pin RA2 (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC32MX170F256B-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC32MX170F256B-I/ML (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC32MX170F256B-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC32MX170F256B-I/ML (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & PIC32MX250F1 / PIC32MX170F2 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	PGED1	Digital_IO	Signal terminal PGED1 (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: PGED1. Supported peripheral buses: General.
2	PGEC1	Digital_IO	Signal terminal PGEC1 (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: PGEC1. Supported peripheral buses: General.
3	CTED13	Digital_IO	Signal terminal CTED13 (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: CTED13. Supported peripheral buses: General.
4	C2INC	Digital_IO	Signal terminal C2INC (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: C2INC. Supported peripheral buses: General.
5	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
6	RA2	Digital_IO	Signal terminal RA2 (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: RA2. Supported peripheral buses: General.
7	RA3	Digital_IO	Signal terminal RA3 (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: RA3. Supported peripheral buses: General.
8	PMA0	Digital_IO	Signal terminal PMA0 (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: PMA0. Supported peripheral buses: General.
9	CTED9	Digital_IO	Signal terminal CTED9 (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: CTED9. Supported peripheral buses: General.
10	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.3V to 3.6V domain (Max rating: 3.6V).
11	RB5	Digital_IO	Signal terminal RB5 (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: RB5. Supported peripheral buses: General.
12	PGEC3/RPB6/PMD6/RB6	Digital_IO	Signal terminal PGEC3/RPB6/PMD6/RB6 (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: PGEC3/RPB6/PMD6/RB6. Supported peripheral buses: General.
13	CTED3	Digital_IO	Signal terminal CTED3 (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: CTED3. Supported peripheral buses: General.
14	CTED10	Digital_IO	Signal terminal CTED10 (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: CTED10. Supported peripheral buses: General.
15	CTED4	Digital_IO	Signal terminal CTED4 (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: CTED4. Supported peripheral buses: General.
16	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
17	VCAP	Digital_IO	Signal terminal VCAP (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
18	PGED2	Digital_IO	Signal terminal PGED2 (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: PGED2. Supported peripheral buses: General.
19	PGEC2	Digital_IO	Signal terminal PGEC2 (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: PGEC2. Supported peripheral buses: General.
20	AN12/PMD0/RB12	Digital_IO	Signal terminal AN12/PMD0/RB12 (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: AN12/PMD0/RB12. Supported peripheral buses: General.
21	CTPLS	Digital_IO	Signal terminal CTPLS (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: CTPLS. Supported peripheral buses: General.
22	CTED5	Digital_IO	Signal terminal CTED5 (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: CTED5. Supported peripheral buses: General.
23	CTED6	Digital_IO	Signal terminal CTED6 (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: CTED6. Supported peripheral buses: General.
24	AVSS	GND	0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
25	AVDD	Power_In	Primary positive power supply input (AVDD) operating in the 2.3V to 3.6V domain (Max rating: 3.6V).
26	MCLR	Digital_IO	Signal terminal MCLR (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: MCLR. Supported peripheral buses: General.
27	VREF+	Analog	Signal terminal VREF+ (Analog, 2.3V to 3.6V domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
28	VREF-	Analog	Signal terminal VREF- (Analog, 2.3V to 3.6V domain). Multiplexed alternate functions: VREF-. Supported peripheral buses: General.
29	PMCS1	Digital_IO	Signal terminal PMCS1 (I/O, 2.3V to 3.6V domain). Multiplexed alternate functions: PMCS1. Supported peripheral buses: General.

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