PIC16F767-I/ML (QFN-28-EP(6x6)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of PIC16F767-I/ML (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the PIC16F767-I/ML is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.7V-3.3V. Key pins include: 1 (RA2/AN2/VREF-/CVREF: Multiplexed I/O & Peripheral Pin RA2/AN2/VREF-/CVREF (General)), 2 (RA3/AN3/VREF+: Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)), 3 (RA4/T0CKI/C1OUT: Multiplexed I/O & Peripheral Pin RA4/T0CKI/C1OUT (General)), 4 (NC: No Connect (Leave Floating)), 5 (VSS: Ground Reference Pin (VSS)), 6 (OSC1/CLKI/RA7: Multiplexed I/O & Peripheral Pin OSC1/CLKI/RA7 (RTC/CLK)).

Q: What are the IPC-7351B PCB Footprint dimensions for PIC16F767-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16F767-I/ML (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16F767-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16F767-I/ML (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 6.00mm × 6.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	RA2/AN2/VREF-/CVREF	Analog	Multiplexed I/O & Peripheral Pin RA2/AN2/VREF-/CVREF (General)
2	RA3/AN3/VREF+	Analog	Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)
3	RA4/T0CKI/C1OUT	I/O	Multiplexed I/O & Peripheral Pin RA4/T0CKI/C1OUT (General)
4	NC	NC	No Connect (Leave Floating)
5	VSS	GND	Ground Reference Pin (VSS)
6	OSC1/CLKI/RA7	I/O	Multiplexed I/O & Peripheral Pin OSC1/CLKI/RA7 (RTC/CLK)
7	OSC2/CLKO/RA6	I/O	Multiplexed I/O & Peripheral Pin OSC2/CLKO/RA6 (RTC/CLK)
8	RC0/T1OSO/T1CKI	I/O	Multiplexed I/O & Peripheral Pin RC0/T1OSO/T1CKI (General)
9	RC1/T1OSI/CCP2	I/O	Multiplexed I/O & Peripheral Pin RC1/T1OSI/CCP2 (General)
10	RC2/CCP1	I/O	Multiplexed I/O & Peripheral Pin RC2/CCP1 (General)
11	RC3/SCK/SCL	I/O	Multiplexed I/O & Peripheral Pin RC3/SCK/SCL (SPI, I2C)
12	RC4/SDI/SDA	I/O	Multiplexed I/O & Peripheral Pin RC4/SDI/SDA (I2C)
13	RC5/SDO	I/O	Multiplexed I/O & Peripheral Pin RC5/SDO (General)
14	RC6/TX/CK	I/O	Multiplexed I/O & Peripheral Pin RC6/TX/CK (General)
15	RC7/RX/DT	I/O	Multiplexed I/O & Peripheral Pin RC7/RX/DT (General)
16	VSS	GND	Ground Reference Pin (VSS)
17	VDD	Power	Power Supply Input (VDD — 2.7V-3.3V)
18	RB0/INT/AN12	I/O	Multiplexed I/O & Peripheral Pin RB0/INT/AN12 (General)
19	RB1/AN10	I/O	Multiplexed I/O & Peripheral Pin RB1/AN10 (General)
20	RB2/AN8	I/O	Multiplexed I/O & Peripheral Pin RB2/AN8 (General)
21	RB3/CCP2/AN9	I/O	Multiplexed I/O & Peripheral Pin RB3/CCP2/AN9 (General)
22	RB4/AN11	I/O	Multiplexed I/O & Peripheral Pin RB4/AN11 (General)
23	RB5/AN13/CCP3	I/O	Multiplexed I/O & Peripheral Pin RB5/AN13/CCP3 (General)
24	RB6/PGC	I/O	Multiplexed I/O & Peripheral Pin RB6/PGC (General)
25	RB7/PGD	I/O	Multiplexed I/O & Peripheral Pin RB7/PGD (General)
26	MCLR#/VPP/RE3	I/O	Multiplexed I/O & Peripheral Pin MCLR#/VPP/RE3 (General)
27	RA0/AN0	I/O	Multiplexed I/O & Peripheral Pin RA0/AN0 (General)
28	RA1/AN1	I/O	Multiplexed I/O & Peripheral Pin RA1/AN1 (General)
29	EP	GND	Exposed Thermal & Ground Pad (EP)

PIN 1 RA2/AN2/VREF-/CVREF

Analog

Multiplexed I/O & Peripheral Pin RA2/AN2/VREF-/CVREF (General)

Design note: Signal terminal RA2/AN2/VREF-/CVREF (Analog, 2.7V-3.3V domain). Multiplexed alternate functions: RA2/AN2/VREF-/CVREF. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

PIC16F767-I/ML (QFN-28-EP(6x6)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

PIC16F767-I/ML (QFN-28-EP(6x6)) - 2. Standard Pinout (Top View)

True package pinout (29 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

PIC16F767-I/ML (QFN-28-EP(6x6)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

PIC16F767-I/ML (QFN-28-EP(6x6)) - 4. Package Dimensions (D×E×A)

QFN-28-EP(6x6) · 6.00×6.00mm · Pitch 0.65mmExpand ›

5. Recommended Land PatternLAND PATTERN

PIC16F767-I/ML (QFN-28-EP(6x6)) - 5. Recommended Land Pattern

IPC-7351B Footprint (29 Pads)Expand ›

6. Application SchematicSCHEMATIC

PIC16F767-I/ML (QFN-28-EP(6x6)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)

Showing 1–10 of 10 uncropped original figures for PIC16F767 / PIC16F777

P2 · p02_fig01967×917px

QFN (28-pin)

P2 · p02_fig021356×834px

44 43 42 41 40 39 16 17

P2 · p02_fig031352×990px

PIC16F767

P89 · p89_fig01867×606px

FIGURE 9-1: CAPTURE MODE OPERATION BLOCK DIAGRAM

P89 · p89_fig02867×775px

FIGURE 9-2: COMPARE MODE OPERATION BLOCK DIAGRAM

P97 · p97_fig011777×938px

FIGURE 10-2: SPI MASTER/SLAVE CONNECTION

P108 · p108_fig01738×2217px

FIGURE 10-8: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)

P109 · p109_fig011085×2300px

FIGURE 10-9: I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)

P109 · p109_fig01P109

Datasheet Page 109 (p109_fig01)

P249 · p249_fig011777×2564px

PIC16F7X7

Technical Specifications & Part Details (PIC16F767-I/ML)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:PIC16F767-I/ML (QFN-28-EP(6x6)) is a 28-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 2.7V-3.3V supply operation across -40°C to +85°C with integrated SPI, I2C, ADC, PWM, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

2.7V-3.3V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to +85°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

1 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

6.00 × 6.00 × 1.00 mm (A1=0.03 mm)

Package family: QFN (QFN-28-EP(6x6))

Pin Count & Lead PitchN / e

28 Pins | Pitch e = 0.65 mm (25.6 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

SPI, I2C, ADC, PWM, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol29 auto-grouped pins

IPC-7351B Land Pattern29 pads · Pitch 0.65mm

IPC-7525 60% Solder PasteEPAD 4.70×4.70mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

IPC-7351B

Family Variants & Same Datasheet Chips — PIC16F767 / PIC16F777 (2)

Select package variant or sibling MPN sharing this datasheet

QFN-28-EP(6x6) · 29P

PIC16F767-I/ML

MICROCHIP·QFN-28-EP(6x6)

IPC-7351B

29P6.0×6.0×1.00mmP=0.65mm

PIC16F767 / PIC16F777 (QFN-28-EP(6x6))

TQFP-44(10x10) · 44P

PIC16F777-I/PT

MICROCHIP·TQFP-44(10x10)

IPC-7351B

44P10.0×10.0×1.20mmP=0.8mm

PIC16F767 / PIC16F777 (TQFP-44(10x10))

Mechanical Dimensions & Land Pattern (QFN-28-EP(6x6))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

6.00 × 6.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.00mm · e=0.65mm

Pad Size (W × L)Level B

0.28 × 0.80 mm

Pins / Total PadsTopology

29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit QFN-28-EP(6x6)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC16F767-I/ML (QFN-28-EP(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC16F767-I/ML (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the PIC16F767-I/ML is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.7V-3.3V. Key pins include: 1 (RA2/AN2/VREF-/CVREF: Multiplexed I/O & Peripheral Pin RA2/AN2/VREF-/CVREF (General)), 2 (RA3/AN3/VREF+: Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)), 3 (RA4/T0CKI/C1OUT: Multiplexed I/O & Peripheral Pin RA4/T0CKI/C1OUT (General)), 4 (NC: No Connect (Leave Floating)), 5 (VSS: Ground Reference Pin (VSS)), 6 (OSC1/CLKI/RA7: Multiplexed I/O & Peripheral Pin OSC1/CLKI/RA7 (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for PIC16F767-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16F767-I/ML (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16F767-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16F767-I/ML (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & PIC16F767 / PIC16F777 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	RA2/AN2/VREF-/CVREF	Analog	Signal terminal RA2/AN2/VREF-/CVREF (Analog, 2.7V-3.3V domain). Multiplexed alternate functions: RA2/AN2/VREF-/CVREF. Supported peripheral buses: General.
2	RA3/AN3/VREF+	Analog	Signal terminal RA3/AN3/VREF+ (Analog, 2.7V-3.3V domain). Multiplexed alternate functions: RA3/AN3/VREF+. Supported peripheral buses: General.
3	RA4/T0CKI/C1OUT	Digital_IO	Signal terminal RA4/T0CKI/C1OUT (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RA4/T0CKI/C1OUT. Supported peripheral buses: General.
4	NC	No_Connect	No Connect (Leave Floating)
5	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
6	OSC1/CLKI/RA7	Digital_IO	Signal terminal OSC1/CLKI/RA7 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: OSC1/CLKI/RA7. Supported peripheral buses: RTC/CLK.
7	OSC2/CLKO/RA6	Digital_IO	Signal terminal OSC2/CLKO/RA6 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: OSC2/CLKO/RA6. Supported peripheral buses: RTC/CLK.
8	RC0/T1OSO/T1CKI	Digital_IO	Signal terminal RC0/T1OSO/T1CKI (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RC0/T1OSO/T1CKI. Supported peripheral buses: General.
9	RC1/T1OSI/CCP2	Digital_IO	Signal terminal RC1/T1OSI/CCP2 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RC1/T1OSI/CCP2. Supported peripheral buses: General.
10	RC2/CCP1	Digital_IO	Signal terminal RC2/CCP1 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RC2/CCP1. Supported peripheral buses: General.
11	RC3/SCK/SCL	Digital_IO	Signal terminal RC3/SCK/SCL (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RC3/SCK/SCL. Supported peripheral buses: SPI, I2C.
12	RC4/SDI/SDA	Digital_IO	Signal terminal RC4/SDI/SDA (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RC4/SDI/SDA. Supported peripheral buses: I2C.
13	RC5/SDO	Digital_IO	Signal terminal RC5/SDO (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RC5/SDO. Supported peripheral buses: General.
14	RC6/TX/CK	Digital_IO	Signal terminal RC6/TX/CK (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RC6/TX/CK. Supported peripheral buses: General.
15	RC7/RX/DT	Digital_IO	Signal terminal RC7/RX/DT (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RC7/RX/DT. Supported peripheral buses: General.
16	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
17	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.7V-3.3V domain (Max rating: 3.3V).
18	RB0/INT/AN12	Digital_IO	Signal terminal RB0/INT/AN12 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RB0/INT/AN12. Supported peripheral buses: General.
19	RB1/AN10	Digital_IO	Signal terminal RB1/AN10 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RB1/AN10. Supported peripheral buses: General.
20	RB2/AN8	Digital_IO	Signal terminal RB2/AN8 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RB2/AN8. Supported peripheral buses: General.
21	RB3/CCP2/AN9	Digital_IO	Signal terminal RB3/CCP2/AN9 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RB3/CCP2/AN9. Supported peripheral buses: General.
22	RB4/AN11	Digital_IO	Signal terminal RB4/AN11 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RB4/AN11. Supported peripheral buses: General.
23	RB5/AN13/CCP3	Digital_IO	Signal terminal RB5/AN13/CCP3 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RB5/AN13/CCP3. Supported peripheral buses: General.
24	RB6/PGC	Digital_IO	Signal terminal RB6/PGC (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RB6/PGC. Supported peripheral buses: General.
25	RB7/PGD	Digital_IO	Signal terminal RB7/PGD (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RB7/PGD. Supported peripheral buses: General.
26	MCLR#/VPP/RE3	Digital_IO	Signal terminal MCLR#/VPP/RE3 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: MCLR#/VPP/RE3. Supported peripheral buses: General.
27	RA0/AN0	Digital_IO	Signal terminal RA0/AN0 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RA0/AN0. Supported peripheral buses: General.
28	RA1/AN1	Digital_IO	Signal terminal RA1/AN1 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RA1/AN1. Supported peripheral buses: General.
29	EP	GND	Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.

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