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HV56020T-V/KXX (VQFN-43-EP(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

HV56020T-V/KXX

MICROCHIPID: C1858324VQFN-43-EP(7x7) · 45 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · HV56020T-V/KXX (VQFN-43-EP(7x7))1HVGND2CCP2+3CCP2 -4CCP1+5CCP1 -6V IN7V LL8SCK9SDI10SDO11SS12HVGND13RT14TON15SHDN16V 0 IN17V 1 IN18HVGND19R BIAS20Timer021Comp022Timer123Comp145D44HVGND43PGND42VDD41EN_CP40FB39SHT -38SHT+37D36S35S34S33S32D31D30D29D28HVGND27HV 0 OUT26V PP25HV 1 OUT24V CCGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.835.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112252627282930314342414039383736353433321314151617181920212223244544E=7.00mm · Pitch e=0.50mmD=7.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (45/45)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1HVGNDGNDGround Reference Pin (HVGND)
2CCP2+I/OMultiplexed I/O & Peripheral Pin CCP2+ (General)
3CCP2 -I/OMultiplexed I/O & Peripheral Pin CCP2 - (General)
4CCP1+I/OMultiplexed I/O & Peripheral Pin CCP1+ (General)
5CCP1 -I/OMultiplexed I/O & Peripheral Pin CCP1 - (General)
6V INI/OMultiplexed I/O & Peripheral Pin V IN (General)
7V LLI/OMultiplexed I/O & Peripheral Pin V LL (General)
8SCKI/OMultiplexed I/O & Peripheral Pin SCK (SPI)
9SDII/OMultiplexed I/O & Peripheral Pin SDI (SPI)
10SDOI/OMultiplexed I/O & Peripheral Pin SDO (SPI)
11SSI/OMultiplexed I/O & Peripheral Pin SS (SPI)
12HVGNDGNDGround Reference Pin (HVGND)
13RTI/OMultiplexed I/O & Peripheral Pin RT (General)
14TONI/OMultiplexed I/O & Peripheral Pin TON (General)
15SHDNI/OMultiplexed I/O & Peripheral Pin SHDN (General)
16V 0 INI/OMultiplexed I/O & Peripheral Pin V 0 IN (General)
17V 1 INI/OMultiplexed I/O & Peripheral Pin V 1 IN (General)
18HVGNDGNDGround Reference Pin (HVGND)
19R BIASI/OMultiplexed I/O & Peripheral Pin R BIAS (General)
20Timer0I/OMultiplexed I/O & Peripheral Pin Timer0 (General)
21Comp0I/OMultiplexed I/O & Peripheral Pin Comp0 (General)
22Timer1I/OMultiplexed I/O & Peripheral Pin Timer1 (General)
23Comp1I/OMultiplexed I/O & Peripheral Pin Comp1 (General)
24V CCI/OMultiplexed I/O & Peripheral Pin V CC (General)
25HV 1 OUTI/OMultiplexed I/O & Peripheral Pin HV 1 OUT (General)
26V PPI/OMultiplexed I/O & Peripheral Pin V PP (General)
27HV 0 OUTI/OMultiplexed I/O & Peripheral Pin HV 0 OUT (General)
28HVGNDGNDGround Reference Pin (HVGND)
29DI/OMultiplexed I/O & Peripheral Pin D (General)
30DI/OMultiplexed I/O & Peripheral Pin D (General)
31DI/OMultiplexed I/O & Peripheral Pin D (General)
32DI/OMultiplexed I/O & Peripheral Pin D (General)
33SI/OMultiplexed I/O & Peripheral Pin S (General)
34SI/OMultiplexed I/O & Peripheral Pin S (General)
35SI/OMultiplexed I/O & Peripheral Pin S (General)
36SI/OMultiplexed I/O & Peripheral Pin S (General)
37DI/OMultiplexed I/O & Peripheral Pin D (General)
38SHT+I/OMultiplexed I/O & Peripheral Pin SHT+ (General)
39SHT -I/OMultiplexed I/O & Peripheral Pin SHT - (General)
40FBI/OMultiplexed I/O & Peripheral Pin FB (General)
41EN_CPI/OMultiplexed I/O & Peripheral Pin EN_CP (General)
42VDDPowerRegulated Power Output (VDD — 2.7V to 5.5V)
43PGNDGNDGround Reference Pin (PGND)
44HVGNDGNDGround Reference Pin (HVGND)
45DI/OMultiplexed I/O & Peripheral Pin D (General)
PIN 1 HVGND
GND
Ground Reference Pin (HVGND)
Design note: HighVoltageGround
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: HV56020T-V/KXX (MICROCHIP · VQFN-43-EP(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
HV56020T-V/KXX (VQFN-43-EP(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
HV56020T-V/KXX (VQFN-43-EP(7x7)) - 2. Standard Pinout (Top View)
True package pinout (45 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
HV56020T-V/KXX (VQFN-43-EP(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
HV56020T-V/KXX (VQFN-43-EP(7x7)) - 4. Package Dimensions (D×E×A)
VQFN-43-EP(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
HV56020T-V/KXX (VQFN-43-EP(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (45 Pads)Expand ›
6. Application SchematicSCHEMATIC
HV56020T-V/KXX (VQFN-43-EP(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)
Showing 1–12 of 15 uncropped original figures for HV56020
P1 · p01_fig01376×200px
HV56020T-V/KXX (VQFN-43-EP(7x7)) — Dual High Voltage Op Amp with Step-Up Converter and Power MOSFET
Dual High Voltage Op Amp with Step-Up Converter and Power MOSFET
P1 · p01_fig02868×1135px
HV56020T-V/KXX (VQFN-43-EP(7x7)) —  2020 Microchip Technology Inc. DS20006335A-page 1
 2020 Microchip Technology Inc. DS20006335A-page 1
P2 · p02_fig011917×1645px
HV56020T-V/KXX (VQFN-43-EP(7x7)) — HV56020 | Block Diagram | HVGND | RBIAS | + | -comp | Offset & | Delay comp | + | -comp | Offset & | Delay comp | CCP2 | CCP1 | Regulated Charge Pump | Converter | DC-to-DC Controller | GATE DRIVER | Power MOSFET | VPP SHT+ FB D VIN | HVOUT
HV56020 | Block Diagram | HVGND | RBIAS | + | -comp | Offset & | Delay comp | + | -comp | Offset & | Delay comp | CCP2 | CCP1 | Regulated Charge Pump | Converter | DC-to-DC Controller | GATE DRIVER | Power MOSFET | VPP SHT+ FB D VIN | HVOUT
P15 · p15_fig011773×1831px
HV56020T-V/KXX (VQFN-43-EP(7x7)) — FIGURE 3-1: VQFN 43-Lead 7 x 7 mm.
FIGURE 3-1: VQFN 43-Lead 7 x 7 mm.
P15 · p15_fig01P15
HV56020T-V/KXX (VQFN-43-EP(7x7)) — Datasheet Page 15 (p15_fig01)
Datasheet Page 15 (p15_fig01)
P29 · p29_fig011559×964px
HV56020T-V/KXX (VQFN-43-EP(7x7)) — FIGURE 5-1: Application Block Diagram.
FIGURE 5-1: Application Block Diagram.
P30 · p30_fig011633×917px
HV56020T-V/KXX (VQFN-43-EP(7x7)) — FIGURE 5-2: HV56020 PCB Layout Diagram.
FIGURE 5-2: HV56020 PCB Layout Diagram.
P32 · p32_fig011651×684px
HV56020T-V/KXX (VQFN-43-EP(7x7)) — XXXXXXX | YYWWNNN | HV56020 | 2012256 | 3 e | 43-Lead VQFN Example
XXXXXXX | YYWWNNN | HV56020 | 2012256 | 3 e | 43-Lead VQFN Example
P32 · p32_fig02687×547px
HV56020T-V/KXX (VQFN-43-EP(7x7)) — 43-Lead VQFN Example
43-Lead VQFN Example
P32 · p32_fig03688×547px
HV56020T-V/KXX (VQFN-43-EP(7x7)) — 43-Lead VQFN Example
43-Lead VQFN Example
P32 · p32_fig041361×616px
HV56020T-V/KXX (VQFN-43-EP(7x7)) — Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. | 3 e | 3 e
Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. | 3 e | 3 e
P34 · p34_fig011778×2729px
HV56020T-V/KXX (VQFN-43-EP(7x7)) — HV56020 | DS20006335A-page 34  2020 Microchip Technology Inc. | Microchip Technology Drawing C04-471 Rev. A Sheet 2 of 2 | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microc
HV56020 | DS20006335A-page 34  2020 Microchip Technology Inc. | Microchip Technology Drawing C04-471 Rev. A Sheet 2 of 2 | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microc
Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (HV56020T-V/KXX)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:HV56020T-V/KXX (VQFN-43-EP(7x7)) is a 43-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.7V to 5.5V supply operation across -55°C to +150°C with integrated SPI, DAC, PWM interfaces.
Operating Supply VoltageV_CC / V_DD
2.7V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-55°C to +150°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
24 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (VQFN-43-EP(7x7))
Pin Count & Lead PitchN / e
43 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, DAC, PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol45 auto-grouped pins
OK
IPC-7351B Land Pattern45 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 5.26×6.90mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (VQFN-43-EP(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.50mm
Pad Size (W × L)Level B
0.25 × 0.85 mm
Pins / Total PadsTopology
45P / 45Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
VQFN-43-EP(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — HV56020T-V/KXX (VQFN-43-EP(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of HV56020T-V/KXX (VQFN-43-EP(7x7))?

Manufactured by MICROCHIP, the HV56020T-V/KXX is housed in a VQFN-43-EP(7x7) package with 45 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.7V to 5.5V. Key pins include: 1 (HVGND: Ground Reference Pin (HVGND)), 2 (CCP2+: Multiplexed I/O & Peripheral Pin CCP2+ (General)), 3 (CCP2 -: Multiplexed I/O & Peripheral Pin CCP2 - (General)), 4 (CCP1+: Multiplexed I/O & Peripheral Pin CCP1+ (General)), 5 (CCP1 -: Multiplexed I/O & Peripheral Pin CCP1 - (General)), 6 (V IN: Multiplexed I/O & Peripheral Pin V IN (General)).

What are the IPC-7351B PCB Footprint dimensions for HV56020T-V/KXX?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), HV56020T-V/KXX (VQFN-43-EP(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 45 copper pads plus a central exposed thermal pad (EPAD) of 5.26 × 6.90 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for HV56020T-V/KXX?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for HV56020T-V/KXX (MICROCHIP, VQFN-43-EP(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (45 pins) & HV56020 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
2CCP2+Digital_IOSignal terminal CCP2+ (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: CCP2+. Supported peripheral buses: General.
3CCP2 -Digital_IOSignal terminal CCP2 - (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: CCP2 -. Supported peripheral buses: General.
4CCP1+Digital_IOSignal terminal CCP1+ (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: CCP1+. Supported peripheral buses: General.
5CCP1 -Digital_IOSignal terminal CCP1 - (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: CCP1 -. Supported peripheral buses: General.
6V INDigital_IOSignal terminal V IN (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: V IN. Supported peripheral buses: General.
7V LLDigital_IOSignal terminal V LL (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: V LL. Supported peripheral buses: General.
8SCKDigital_IOSignal terminal SCK (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SPICLOCK. Supported peripheral buses: SPI.
9SDIDigital_IOSignal terminal SDI (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SPIDATAINPUT. Supported peripheral buses: SPI.
10SDODigital_IOSignal terminal SDO (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SPIDATAOUTPUT. Supported peripheral buses: SPI.
11SSDigital_IOSignal terminal SS (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SPICHIPSELECT. Supported peripheral buses: SPI.
12HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
13RTDigital_IOSignal terminal RT (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: RT. Supported peripheral buses: General.
14TONDigital_IOSignal terminal TON (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: TON. Supported peripheral buses: General.
15SHDNDigital_IOSignal terminal SHDN (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SHDN. Supported peripheral buses: General.
16V 0 INDigital_IOSignal terminal V 0 IN (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: V 0 IN. Supported peripheral buses: General.
17V 1 INDigital_IOSignal terminal V 1 IN (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: V 1 IN. Supported peripheral buses: General.
18HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
19R BIASDigital_IOSignal terminal R BIAS (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: R BIAS. Supported peripheral buses: General.
20Timer0Digital_IOSignal terminal Timer0 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: Timer0. Supported peripheral buses: General.
21Comp0Digital_IOSignal terminal Comp0 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: Comp0. Supported peripheral buses: General.
22Timer1Digital_IOSignal terminal Timer1 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: Timer1. Supported peripheral buses: General.
23Comp1Digital_IOSignal terminal Comp1 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: Comp1. Supported peripheral buses: General.
24V CCDigital_IOSignal terminal V CC (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: V CC. Supported peripheral buses: General.
25HV 1 OUTDigital_IOSignal terminal HV 1 OUT (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: HV 1 OUT. Supported peripheral buses: General.
26V PPDigital_IOSignal terminal V PP (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: V PP. Supported peripheral buses: General.
27HV 0 OUTDigital_IOSignal terminal HV 0 OUT (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: HV 0 OUT. Supported peripheral buses: General.
28HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
29DDigital_IOSignal terminal D (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: D. Supported peripheral buses: General.
30DDigital_IOSignal terminal D (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: D. Supported peripheral buses: General.
31DDigital_IOSignal terminal D (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: D. Supported peripheral buses: General.
32DDigital_IOSignal terminal D (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: D. Supported peripheral buses: General.
33SDigital_IOSignal terminal S (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: S. Supported peripheral buses: General.
34SDigital_IOSignal terminal S (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: S. Supported peripheral buses: General.
35SDigital_IOSignal terminal S (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: S. Supported peripheral buses: General.
36SDigital_IOSignal terminal S (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: S. Supported peripheral buses: General.
37DDigital_IOSignal terminal D (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: D. Supported peripheral buses: General.
38SHT+Digital_IOSignal terminal SHT+ (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SHT+. Supported peripheral buses: General.
39SHT -Digital_IOSignal terminal SHT - (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SHT -. Supported peripheral buses: General.
40FBDigital_IOSignal terminal FB (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: FB. Supported peripheral buses: General.
41EN_CPDigital_IOSignal terminal EN_CP (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: EN_CP. Supported peripheral buses: General.
42VDDPower_OutRegulated power output rail (VDD) operating in the 2.7V to 5.5V domain (Max rating: 5.5V).
43PGNDGND0V electrical ground return terminal (PGND) for internal core logic, I/O drivers, and analog sub-blocks.
44HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
45DDigital_IOSignal terminal D (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: D. Supported peripheral buses: General.
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