PIC16LF1847-I/SO (SOIC-18-300mil) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of PIC16LF1847-I/SO (SOIC-18-300mil)?

Manufactured by MICROCHIP, the PIC16LF1847-I/SO is housed in a SOIC-18-300mil package with 18 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 1.8V-5.5V. Key pins include: 1 (RA2: Multiplexed I/O & Peripheral Pin RA2 (General)), 2 (RA3: Multiplexed I/O & Peripheral Pin RA3 (General)), 3 (RA4: Multiplexed I/O & Peripheral Pin RA4 (General)), 4 (RA5/MCLR#/VPP: Multiplexed I/O & Peripheral Pin RA5/MCLR#/VPP (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (RB0: Multiplexed I/O & Peripheral Pin RB0 (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for PIC16LF1847-I/SO?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16LF1847-I/SO (SOIC-18-300mil) has a nominal body envelope of 7.50 × 11.55 mm, pitch e = 1.27 mm, and 18 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16LF1847-I/SO?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16LF1847-I/SO (MICROCHIP, SOIC-18-300mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 7.50mm × 11.55mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (18/18)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	RA2	I/O	Multiplexed I/O & Peripheral Pin RA2 (General)
2	RA3	I/O	Multiplexed I/O & Peripheral Pin RA3 (General)
3	RA4	I/O	Multiplexed I/O & Peripheral Pin RA4 (General)
4	RA5/MCLR#/VPP	I/O	Multiplexed I/O & Peripheral Pin RA5/MCLR#/VPP (General)
5	VSS	GND	Ground Reference Pin (VSS)
6	RB0	I/O	Multiplexed I/O & Peripheral Pin RB0 (General)
7	RB1	I/O	Multiplexed I/O & Peripheral Pin RB1 (General)
8	RB2	I/O	Multiplexed I/O & Peripheral Pin RB2 (General)
9	RB3	I/O	Multiplexed I/O & Peripheral Pin RB3 (General)
10	RB4	I/O	Multiplexed I/O & Peripheral Pin RB4 (General)
11	RB5	I/O	Multiplexed I/O & Peripheral Pin RB5 (General)
12	RB6/ICSPCLK	I/O	Multiplexed I/O & Peripheral Pin RB6/ICSPCLK (General)
13	RB7/ICSPDAT	I/O	Multiplexed I/O & Peripheral Pin RB7/ICSPDAT (General)
14	VDD	Power	Power Supply Input (VDD — 1.8V-5.5V)
15	RA6	I/O	Multiplexed I/O & Peripheral Pin RA6 (General)
16	RA7	I/O	Multiplexed I/O & Peripheral Pin RA7 (General)
17	RA0	I/O	Multiplexed I/O & Peripheral Pin RA0 (General)
18	RA1	I/O	Multiplexed I/O & Peripheral Pin RA1 (General)

PIN 1 RA2

I/O

Multiplexed I/O & Peripheral Pin RA2 (General)

Design note: Signal terminal RA2 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: RA2. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

PIC16LF1847-I/SO (SOIC-18-300mil) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

PIC16LF1847-I/SO (SOIC-18-300mil) - 2. Standard Pinout (Top View)

True package pinout (18 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

PIC16LF1847-I/SO (SOIC-18-300mil) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

PIC16LF1847-I/SO (SOIC-18-300mil) - 4. Package Dimensions (D×E×A)

SOIC-18-300mil · 7.50×11.55mm · Pitch 1.27mmExpand ›

5. Recommended Land PatternLAND PATTERN

PIC16LF1847-I/SO (SOIC-18-300mil) - 5. Recommended Land Pattern

IPC-7351B Footprint (18 Pads)Expand ›

6. Application SchematicSCHEMATIC

PIC16LF1847-I/SO (SOIC-18-300mil) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)

Showing 1–12 of 12 uncropped original figures for PIC16LF1847

P397 · p397_fig01EXACT PACKAGE

PIC16(L)F1847

P123 · p123_fig011582×803px

FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM

P198 · p198_fig011536×1053px

FIGURE 24-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)

P198 · p198_fig01P198

Datasheet Page 198 (p198_fig01)

P208 · p208_fig011783×1413px

FIGURE 24-18: SIMPLIFIED STEERING BLOCK DIAGRAM

P311 · p311_fig011416×1013px

FIGURE 28-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING

P311 · p311_fig01P311

Datasheet Page 311 (p311_fig01)

P397 · p397_fig01P397

Datasheet Page 397 (p397_fig01)

P413 · p413_fig011778×2472px

PIC16LF1847-I/SO (SOIC-18-300mil) —  2011-2017 Microchip Technology Inc. DS40001453F-page 413 | RECOMMENDED LAND PATTERN | Dimension Limits | Units | C2 | Optional Center Pad Width | Contact Pad Spacing | Optional Center Pad Length | Contact Pitch | Y2 X2 | 2.75 2.75 | MILLI

P413 · p413_fig01P413

Datasheet Page 413 (p413_fig01)

P1 · p01_fig01All Packages in PDF

18/20/28-Pin Flash Microcontrollers with XLP Technology

P404 · p404_fig01All Packages in PDF

PIC16LF1847-I/SO (SOIC-18-300mil) — DS40001453F-page 404  2011-2017 Microchip Technology Inc. | RECOMMENDED LAND PATTERN | Microchip Technology Drawing No. C04-2072B | 20-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP] | For the most current package drawings, pl

DS40001453F-page 404  2011-2017 Microchip Technology Inc. | RECOMMENDED LAND PATTERN | Microchip Technology Drawing No. C04-2072B | 20-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP] | For the most current package drawings, pl

Technical Specifications & Part Details (PIC16LF1847-I/SO)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:PIC16LF1847-I/SO (SOIC-18-300mil) is a 18-pin standard electronic & interconnect component featuring a 11.55 × 7.50 × 2.70 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V-5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated SPI, I2C, ADC, DAC, PWM interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V-5.5V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

32 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

11.55 × 7.50 × 2.70 mm (A1=0.20 mm)

Package family: SOIC (SOIC-18-300mil)

Pin Count & Lead PitchN / e

18 Pins | Pitch e = 1.27 mm (50.0 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

SPI, I2C, ADC, DAC, PWM

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol18 auto-grouped pins

IPC-7351B Land Pattern18 pads · Pitch 1.27mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOIC-18-300mil)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

11.55 × 7.50 mm

Height (A) & Pitch (e)IPC-7351B

A=2.70mm · e=1.27mm

Pad Size (W × L)Level B

0.60 × 1.90 mm

Pins / Total PadsTopology

18P / 18Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit SOIC-18-300mil	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC16LF1847-I/SO (SOIC-18-300mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC16LF1847-I/SO (SOIC-18-300mil)?

Manufactured by MICROCHIP, the PIC16LF1847-I/SO is housed in a SOIC-18-300mil package with 18 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 1.8V-5.5V. Key pins include: 1 (RA2: Multiplexed I/O & Peripheral Pin RA2 (General)), 2 (RA3: Multiplexed I/O & Peripheral Pin RA3 (General)), 3 (RA4: Multiplexed I/O & Peripheral Pin RA4 (General)), 4 (RA5/MCLR#/VPP: Multiplexed I/O & Peripheral Pin RA5/MCLR#/VPP (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (RB0: Multiplexed I/O & Peripheral Pin RB0 (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC16LF1847-I/SO?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16LF1847-I/SO (SOIC-18-300mil) has a nominal body envelope of 7.50 × 11.55 mm, pitch e = 1.27 mm, and 18 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16LF1847-I/SO?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16LF1847-I/SO (MICROCHIP, SOIC-18-300mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (18 pins) & PIC16LF1847 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	RA2	Digital_IO	Signal terminal RA2 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: RA2. Supported peripheral buses: General.
2	RA3	Digital_IO	Signal terminal RA3 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: RA3. Supported peripheral buses: General.
3	RA4	Digital_IO	Signal terminal RA4 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: RA4. Supported peripheral buses: General.
4	RA5/MCLR#/VPP	Digital_IO	Signal terminal RA5/MCLR#/VPP (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: RA5/MCLR#/VPP. Supported peripheral buses: General.
5	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
6	RB0	Digital_IO	Signal terminal RB0 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: RB0. Supported peripheral buses: General.
7	RB1	Digital_IO	Signal terminal RB1 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: RB1. Supported peripheral buses: General.
8	RB2	Digital_IO	Signal terminal RB2 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: RB2. Supported peripheral buses: General.
9	RB3	Digital_IO	Signal terminal RB3 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: RB3. Supported peripheral buses: General.
10	RB4	Digital_IO	Signal terminal RB4 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: RB4. Supported peripheral buses: General.
11	RB5	Digital_IO	Signal terminal RB5 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: RB5. Supported peripheral buses: General.
12	RB6/ICSPCLK	Digital_IO	Signal terminal RB6/ICSPCLK (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: RB6/ICSPCLK. Supported peripheral buses: General.
13	RB7/ICSPDAT	Digital_IO	Signal terminal RB7/ICSPDAT (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: RB7/ICSPDAT. Supported peripheral buses: General.
14	VDD	Power_In	Primary positive power supply input (VDD) operating in the 1.8V-5.5V domain (Max rating: 5.5V).
15	RA6	Digital_IO	Signal terminal RA6 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: RA6. Supported peripheral buses: General.
16	RA7	Digital_IO	Signal terminal RA7 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: RA7. Supported peripheral buses: General.
17	RA0	Digital_IO	Signal terminal RA0 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: RA0. Supported peripheral buses: General.
18	RA1	Digital_IO	Signal terminal RA1 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: RA1. Supported peripheral buses: General.

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