MCP6294-E/ST (TSSOP-14) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of MCP6294-E/ST (TSSOP-14)?

Manufactured by MICROCHIP, the MCP6294-E/ST is housed in a TSSOP-14 package with 14 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.4V to 6.0V. Key pins include: 1 (V OUTA: Multiplexed I/O & Peripheral Pin V OUTA (General)), 2 (V INA–: Multiplexed I/O & Peripheral Pin V INA– (General)), 3 (V INA+: Multiplexed I/O & Peripheral Pin V INA+ (General)), 4 (VSS: Ground Reference Pin (VSS)), 5 (V INB+: Multiplexed I/O & Peripheral Pin V INB+ (General)), 6 (V INB–: Multiplexed I/O & Peripheral Pin V INB– (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for MCP6294-E/ST?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MCP6294-E/ST (TSSOP-14) has a nominal body envelope of 4.40 × 5.00 mm, pitch e = 0.65 mm, and 14 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MCP6294-E/ST?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MCP6294-E/ST (MICROCHIP, TSSOP-14) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 4.40mm × 5.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (14/14)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	V OUTA	I/O	Multiplexed I/O & Peripheral Pin V OUTA (General)
2	V INA–	I/O	Multiplexed I/O & Peripheral Pin V INA– (General)
3	V INA+	I/O	Multiplexed I/O & Peripheral Pin V INA+ (General)
4	VSS	GND	Ground Reference Pin (VSS)
5	V INB+	I/O	Multiplexed I/O & Peripheral Pin V INB+ (General)
6	V INB–	I/O	Multiplexed I/O & Peripheral Pin V INB– (General)
7	V OUTB	I/O	Multiplexed I/O & Peripheral Pin V OUTB (General)
8	VDD	Power	Power Supply Input (VDD — 2.4V to 6.0V)
9	VINC-	Power	Power Supply Input (VINC- — 2.4V to 6.0V)
10	VINC+	Power	Power Supply Input (VINC+ — 2.4V to 6.0V)
11	VSS	GND	Ground Reference Pin (VSS)
12	VIND+	Power	Power Supply Input (VIND+ — 2.4V to 6.0V)
13	VIND-	Power	Power Supply Input (VIND- — 2.4V to 6.0V)
14	VOUTD	Power	Power Supply Input (VOUTD — 2.4V to 6.0V)

PIN 1 V OUTA

I/O

Multiplexed I/O & Peripheral Pin V OUTA (General)

Design note: AnalogOutput(opampA)

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

MCP6294-E/ST (TSSOP-14) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

MCP6294-E/ST (TSSOP-14) - 2. Standard Pinout (Top View)

True package pinout (14 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

MCP6294-E/ST (TSSOP-14) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

MCP6294-E/ST (TSSOP-14) - 4. Package Dimensions (D×E×A)

TSSOP-14 · 4.40×5.00mm · Pitch 0.65mmExpand ›

5. Recommended Land PatternLAND PATTERN

MCP6294-E/ST (TSSOP-14) - 5. Recommended Land Pattern

IPC-7351B Footprint (14 Pads)Expand ›

6. Application SchematicSCHEMATIC

MCP6294-E/ST (TSSOP-14) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)

Showing 1–11 of 11 uncropped original figures for MCP6294

P1 · p01_fig011777×1021px

MCP6294-E/ST (TSSOP-14) — © 2007 Microchip Technology Inc. DS21812E-page 1 | • SPICE Macro Models • FilterLab® Software • Mindi™ Simulation Tool • MAPS (Microchip Advanced Part Selector) • Analog Demonstration and Evaluation Boards • Application Notes | Package Type

© 2007 Microchip Technology Inc. DS21812E-page 1 | • SPICE Macro Models • FilterLab® Software • Mindi™ Simulation Tool • MAPS (Microchip Advanced Part Selector) • Analog Demonstration and Evaluation Boards • Application Notes | Package Type

P12 · p12_fig01867×702px

FIGURE 4-2: Protecting the Analog Inputs.

P12 · p12_fig021543×591px

FIGURE 4-1: Simplified Analog Input ESD Structures.

P14 · p14_fig011777×843px

FIGURE 4-6: Unused Op Amps.

P15 · p15_fig011417×565px

MCP6294-E/ST (TSSOP-14) — FIGURE 4-8: Multiple Feedback Low- Pass Filter. This filter, and others, can be designed using Microchip’s Filter design software. Refer to Section 5.0 “Design Aids”

FIGURE 4-8: Multiple Feedback Low- Pass Filter. This filter, and others, can be designed using Microchip’s Filter design software. Refer to Section 5.0 “Design Aids”

P15 · p15_fig02867×478px

FIGURE 4-8: Multiple Feedback Low- Pass Filter. This filter, and others, can be designed using Microchip’s Filter design software. Refer to Section 5.0 “Design Aids”

P15 · p15_fig03867×566px

FIGURE 4-10: Isolating the Load with a Buffer.

P15 · p15_fig01P15

Datasheet Page 15 (p15_fig01)

P19 · p19_fig01All Packages in PDF

MCP6294-E/ST (TSSOP-14) — © 2007 Microchip Technology Inc. DS21812E-page 19 | MCP6291/1R/2/3/4/5 | 6.0 PACKAGING INFORMATION | 6.1 Package Marking Information | XXXXXXXX XXXXXNNN | YYWW | 8-Lead PDIP (300 mil) Example: | 8-Lead SOIC (150 mil) Example: | XXXXXXXX XXX

P25 · p25_fig01All Packages in PDF

MCP6294-E/ST (TSSOP-14) — 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] - Note: For the most current package drawings, please see the Microchip Packaging Specification located at - http:/www.microchip.com/packaging | © 2007 Microchip Technology Inc

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] - Note: For the most current package drawings, please see the Microchip Packaging Specification located at - http:/www.microchip.com/packaging | © 2007 Microchip Technology Inc

P28 · p28_fig01All Packages in PDF

MCP6294-E/ST (TSSOP-14) — 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] - Note: For the most current package drawings, please see the Microchip Packaging Specification located at - http://www.microchip.com/packaging | MCP6291/1R/2/3/4/5 | DS21812E

14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] - Note: For the most current package drawings, please see the Microchip Packaging Specification located at - http://www.microchip.com/packaging | MCP6291/1R/2/3/4/5 | DS21812E

Technical Specifications & Part Details (MCP6294-E/ST)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:MCP6294-E/ST (TSSOP-14) is a 14-pin standard electronic & interconnect component featuring a 5.00 × 4.40 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 2.4V to 6.0V supply operation across -40°C to +125°C with integrated Standard I/O / Passive interfaces.

Operating Supply VoltageV_CC / V_DD

2.4V to 6.0V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to +125°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

10 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

1.0 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

5.00 × 4.40 × 1.00 mm (A1=0.10 mm)

Package family: TSSOP (TSSOP-14)

Pin Count & Lead PitchN / e

14 Pins | Pitch e = 0.65 mm (25.6 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

Standard I/O / Passive

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol14 auto-grouped pins

IPC-7351B Land Pattern14 pads · Pitch 0.65mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TSSOP-14)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

5.00 × 4.40 mm

Height (A) & Pitch (e)IPC-7351B

A=1.00mm · e=0.65mm

Pad Size (W × L)Level B

0.42 × 1.45 mm

Pins / Total PadsTopology

14P / 14Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit TSSOP-14	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MCP6294-E/ST (TSSOP-14)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MCP6294-E/ST (TSSOP-14)?

Manufactured by MICROCHIP, the MCP6294-E/ST is housed in a TSSOP-14 package with 14 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.4V to 6.0V. Key pins include: 1 (V OUTA: Multiplexed I/O & Peripheral Pin V OUTA (General)), 2 (V INA–: Multiplexed I/O & Peripheral Pin V INA– (General)), 3 (V INA+: Multiplexed I/O & Peripheral Pin V INA+ (General)), 4 (VSS: Ground Reference Pin (VSS)), 5 (V INB+: Multiplexed I/O & Peripheral Pin V INB+ (General)), 6 (V INB–: Multiplexed I/O & Peripheral Pin V INB– (General)).

What are the IPC-7351B PCB Footprint dimensions for MCP6294-E/ST?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MCP6294-E/ST (TSSOP-14) has a nominal body envelope of 4.40 × 5.00 mm, pitch e = 0.65 mm, and 14 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MCP6294-E/ST?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MCP6294-E/ST (MICROCHIP, TSSOP-14) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (14 pins) & MCP6294 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	V OUTA	Digital_IO	Signal terminal V OUTA (I/O, 2.4V to 6.0V domain). Multiplexed alternate functions: V OUTA. Supported peripheral buses: General.
2	V INA–	Digital_IO	Signal terminal V INA– (I/O, 2.4V to 6.0V domain). Multiplexed alternate functions: V INA–. Supported peripheral buses: General.
3	V INA+	Digital_IO	Signal terminal V INA+ (I/O, 2.4V to 6.0V domain). Multiplexed alternate functions: V INA+. Supported peripheral buses: General.
4	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
5	V INB+	Digital_IO	Signal terminal V INB+ (I/O, 2.4V to 6.0V domain). Multiplexed alternate functions: V INB+. Supported peripheral buses: General.
6	V INB–	Digital_IO	Signal terminal V INB– (I/O, 2.4V to 6.0V domain). Multiplexed alternate functions: V INB–. Supported peripheral buses: General.
7	V OUTB	Digital_IO	Signal terminal V OUTB (I/O, 2.4V to 6.0V domain). Multiplexed alternate functions: V OUTB. Supported peripheral buses: General.
8	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.4V to 6.0V domain (Max rating: 6.0V).
9	VINC-	Power_In	Primary positive power supply input (VINC-) operating in the 2.4V to 6.0V domain (Max rating: 6.0V).
10	VINC+	Power_In	Primary positive power supply input (VINC+) operating in the 2.4V to 6.0V domain (Max rating: 6.0V).
11	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
12	VIND+	Power_In	Primary positive power supply input (VIND+) operating in the 2.4V to 6.0V domain (Max rating: 6.0V).
13	VIND-	Power_In	Primary positive power supply input (VIND-) operating in the 2.4V to 6.0V domain (Max rating: 6.0V).
14	VOUTD	Power_In	Primary positive power supply input (VOUTD) operating in the 2.4V to 6.0V domain (Max rating: 6.0V).

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