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MCP23S17-E/SP (DIP-28) — Symbol, Footprint IPC-7351B & 3D STEP Model

MCP23S17-E/SP

MICROCHIPID: C148096DIP-28 · 28 Pins · Pitch 2.54mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · MCP23S17-E/SP (DIP-28)1GPB02GPB13GPB24GPB35GPB46GPB57GPB68GPB79VDD10VSS11NC/CS12SCK13SDA/SI14NC/SO28GPA727GPA626GPA525GPA424GPA323GPA222GPA121GPA020INTA19INTB18RESET17A216A115A0Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.822.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
12345678910111213142827262524232221201918171615E=34.60mm · Pitch e=2.54mmD=7.30mm-26-24-22-20-18-16-14-12-10-8-6-4-20246810121416182022242614121086420-2-4-6-8-10-12-14mm
3. 3D CAD MODEL
Package Body: 34.60mm × 7.30mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (28/28)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1GPB0I/OMultiplexed I/O & Peripheral Pin GPB0 (CAN)
2GPB1I/OMultiplexed I/O & Peripheral Pin GPB1 (CAN)
3GPB2I/OMultiplexed I/O & Peripheral Pin GPB2 (CAN)
4GPB3I/OMultiplexed I/O & Peripheral Pin GPB3 (CAN)
5GPB4I/OMultiplexed I/O & Peripheral Pin GPB4 (CAN)
6GPB5I/OMultiplexed I/O & Peripheral Pin GPB5 (CAN)
7GPB6I/OMultiplexed I/O & Peripheral Pin GPB6 (CAN)
8GPB7I/OMultiplexed I/O & Peripheral Pin GPB7 (CAN)
9VDDPowerPower Supply Input (VDD — 1.8V to 5.5V)
10VSSGNDGround Reference Pin (VSS)
11NC/CSI/OMultiplexed I/O & Peripheral Pin NC/CS (General)
12SCKI/OMultiplexed I/O & Peripheral Pin SCK (SPI)
13SDA/SII/OMultiplexed I/O & Peripheral Pin SDA/SI (I2C)
14NC/SOI/OMultiplexed I/O & Peripheral Pin NC/SO (General)
15A0I/OMultiplexed I/O & Peripheral Pin A0 (General)
16A1I/OMultiplexed I/O & Peripheral Pin A1 (General)
17A2I/OMultiplexed I/O & Peripheral Pin A2 (General)
18RESETISystem Enable & Hardware Reset (RESET)
19INTBI/OMultiplexed I/O & Peripheral Pin INTB (CAN)
20INTAI/OMultiplexed I/O & Peripheral Pin INTA (CAN)
21GPA0I/OMultiplexed I/O & Peripheral Pin GPA0 (CAN)
22GPA1I/OMultiplexed I/O & Peripheral Pin GPA1 (CAN)
23GPA2I/OMultiplexed I/O & Peripheral Pin GPA2 (CAN)
24GPA3I/OMultiplexed I/O & Peripheral Pin GPA3 (CAN)
25GPA4I/OMultiplexed I/O & Peripheral Pin GPA4 (CAN)
26GPA5I/OMultiplexed I/O & Peripheral Pin GPA5 (CAN)
27GPA6I/OMultiplexed I/O & Peripheral Pin GPA6 (CAN)
28GPA7I/OMultiplexed I/O & Peripheral Pin GPA7 (CAN)
PIN 1 GPB0
I/O
Multiplexed I/O & Peripheral Pin GPB0 (CAN)
Design note: Bidirectional I/O pin Can be enabled for interrupt-on-change and/or internal weak pull -up resistor . .
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: MCP23S17-E/SP (MICROCHIP · DIP-28)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
MCP23S17-E/SP (DIP-28) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
MCP23S17-E/SP (DIP-28) - 2. Standard Pinout (Top View)
True package pinout (28 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
MCP23S17-E/SP (DIP-28) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
MCP23S17-E/SP (DIP-28) - 4. Package Dimensions (D×E×A)
DIP-28 · 34.60×7.30mm · Pitch 2.54mmExpand ›
5. Recommended Land PatternLAND PATTERN
MCP23S17-E/SP (DIP-28) - 5. Recommended Land Pattern
IPC-7351B Footprint (28 Pads)Expand ›
6. Application SchematicSCHEMATIC
MCP23S17-E/SP (DIP-28) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for MCP23S17
P1 · p01_fig02EXACT PACKAGE
MCP23S17-E/SP (DIP-28) — open-drain • INTA and INTB Can Be Configured to Operate Independently or Together
open-drain • INTA and INTB Can Be Configured to Operate Independently or Together
P1 · p01_fig01377×200px
MCP23S17-E/SP (DIP-28) — 16-Bit I/O Expander with Serial Interface
16-Bit I/O Expander with Serial Interface
P1 · p01_fig02P1
MCP23S17-E/SP (DIP-28) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P2 · p02_fig011518×1176px
MCP23S17-E/SP (DIP-28) — Functional Block Diagram
Functional Block Diagram
P26 · p26_fig011777×2564px
MCP23S17-E/SP (DIP-28) — MCP23017/MCP23S17
MCP23017/MCP23S17
P26 · p26_fig02All Packages in PDF
MCP23S17-E/SP (DIP-28) — 28-Lead SOIC Example:
28-Lead SOIC Example:
P26 · p26_fig03All Packages in PDF
MCP23S17-E/SP (DIP-28) — 28-Lead QFN Example:
28-Lead QFN Example:
P26 · p26_fig04All Packages in PDF
MCP23S17-E/SP (DIP-28) — 28-Lead SPDIP Example:
28-Lead SPDIP Example:
P26 · p26_fig05All Packages in PDF
MCP23S17-E/SP (DIP-28) — 28-Lead SPDIP Example:
28-Lead SPDIP Example:

Technical Specifications & Part Details (MCP23S17-E/SP)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:MCP23S17-E/SP (DIP-28) is a 28-pin standard electronic & interconnect component featuring a 34.60 × 7.30 × 4.20 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 1.8V to 5.5V supply operation across -40°C to +85°C with integrated SPI, I2C, CAN interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
100 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
34.60 × 7.30 × 4.20 mm (A1=0.51 mm)
Package family: DIP (DIP-28)
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, I2C, CAN
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol28 auto-grouped pins
OK
IPC-7351B Land Pattern28 pads · Pitch 2.54mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (DIP-28)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
34.60 × 7.30 mm
Height (A) & Pitch (e)IPC-7351B
A=4.20mm · e=2.54mm
Pad Size (W × L)Level B
1.60 × 1.60 mm
Pins / Total PadsTopology
28P / 28Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
DIP-28
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MCP23S17-E/SP (DIP-28)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MCP23S17-E/SP (DIP-28)?

Manufactured by MICROCHIP, the MCP23S17-E/SP is housed in a DIP-28 package with 28 pins and a 2.54 mm lead pitch, supporting a VCC supply range of 1.8V to 5.5V. Key pins include: 1 (GPB0: Multiplexed I/O & Peripheral Pin GPB0 (CAN)), 2 (GPB1: Multiplexed I/O & Peripheral Pin GPB1 (CAN)), 3 (GPB2: Multiplexed I/O & Peripheral Pin GPB2 (CAN)), 4 (GPB3: Multiplexed I/O & Peripheral Pin GPB3 (CAN)), 5 (GPB4: Multiplexed I/O & Peripheral Pin GPB4 (CAN)), 6 (GPB5: Multiplexed I/O & Peripheral Pin GPB5 (CAN)).

What are the IPC-7351B PCB Footprint dimensions for MCP23S17-E/SP?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MCP23S17-E/SP (DIP-28) has a nominal body envelope of 7.30 × 34.60 mm, pitch e = 2.54 mm, and 28 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MCP23S17-E/SP?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MCP23S17-E/SP (MICROCHIP, DIP-28) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (28 pins) & MCP23S17 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1GPB0Digital_IOSignal terminal GPB0 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: GPB0. Supported peripheral buses: CAN.
2GPB1Digital_IOSignal terminal GPB1 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: GPB1. Supported peripheral buses: CAN.
3GPB2Digital_IOSignal terminal GPB2 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: GPB2. Supported peripheral buses: CAN.
4GPB3Digital_IOSignal terminal GPB3 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: GPB3. Supported peripheral buses: CAN.
5GPB4Digital_IOSignal terminal GPB4 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: GPB4. Supported peripheral buses: CAN.
6GPB5Digital_IOSignal terminal GPB5 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: GPB5. Supported peripheral buses: CAN.
7GPB6Digital_IOSignal terminal GPB6 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: GPB6. Supported peripheral buses: CAN.
8GPB7Digital_IOSignal terminal GPB7 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: GPB7. Supported peripheral buses: CAN.
9VDDPower_InPrimary positive power supply input (VDD) operating in the 1.8V to 5.5V domain (Max rating: 5.5V).
10VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
11NC/CSDigital_IOSignal terminal NC/CS (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: NC/CS. Supported peripheral buses: General.
12SCKDigital_IOSignal terminal SCK (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: SCK. Supported peripheral buses: SPI.
13SDA/SIDigital_IOSignal terminal SDA/SI (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: SDA/SI. Supported peripheral buses: I2C.
14NC/SODigital_IOSignal terminal NC/SO (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: NC/SO. Supported peripheral buses: General.
15A0Digital_IOSignal terminal A0 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: A0. Supported peripheral buses: General.
16A1Digital_IOSignal terminal A1 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: A1. Supported peripheral buses: General.
17A2Digital_IOSignal terminal A2 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: A2. Supported peripheral buses: General.
18RESETDigital_IOActive-low hardware reset terminal (RESET): pulling this pin Low resets the processor core and peripherals.
19INTBOpen_DrainSignal terminal INTB (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: INTB. Supported peripheral buses: CAN.
20INTAOpen_DrainSignal terminal INTA (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: INTA. Supported peripheral buses: CAN.
21GPA0Digital_IOSignal terminal GPA0 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: GPA0. Supported peripheral buses: CAN.
22GPA1Digital_IOSignal terminal GPA1 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: GPA1. Supported peripheral buses: CAN.
23GPA2Digital_IOSignal terminal GPA2 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: GPA2. Supported peripheral buses: CAN.
24GPA3Digital_IOSignal terminal GPA3 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: GPA3. Supported peripheral buses: CAN.
25GPA4Digital_IOSignal terminal GPA4 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: GPA4. Supported peripheral buses: CAN.
26GPA5Digital_IOSignal terminal GPA5 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: GPA5. Supported peripheral buses: CAN.
27GPA6Digital_IOSignal terminal GPA6 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: GPA6. Supported peripheral buses: CAN.
28GPA7Digital_IOSignal terminal GPA7 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: GPA7. Supported peripheral buses: CAN.
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