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CH558T (SSOP-20-208mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH558T

WCHID: C139616SSOP-20-208mil · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH558T (SSOP-20-208mil)1P5 1 .2bP4_DRV3bSPI0_PINX_4P5 4 .5P1.7/AIN7/SC6P5.7/RST7P3.2/LED0/IN8P3.4/LEDC/T09P4.6/XI/SCS_10P4.7/XO/SCK_20VDD3319VIN518GND/VSS17P0.2/RXD_16P0.3/TXD_15P5.0/DM14P5.1/DP13P2.7/TXD112P2.6/RXD111P2.5/TNOW/T2Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.217.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=5.30mm · Pitch e=0.65mmD=7.20mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 5.30mm × 7.20mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1P5 1 .I/OMultiplexed I/O & Peripheral Pin P5 1 . (General)
2bP4_DRVI/OMultiplexed I/O & Peripheral Pin bP4_DRV (General)
3bSPI0_PINX_I/OMultiplexed I/O & Peripheral Pin bSPI0_PINX_ (General)
4P5 4 .I/OMultiplexed I/O & Peripheral Pin P5 4 . (General)
5P1.7/AIN7/SCKI/OMultiplexed I/O & Peripheral Pin P1.7/AIN7/SCK (SPI, ADC)
6P5.7/RSTI/OMultiplexed I/O & Peripheral Pin P5.7/RST (General)
7P3.2/LED0/INT0I/OMultiplexed I/O & Peripheral Pin P3.2/LED0/INT0 (General)
8P3.4/LEDC/T0I/OMultiplexed I/O & Peripheral Pin P3.4/LEDC/T0 (General)
9P4.6/XI/SCS_I/OMultiplexed I/O & Peripheral Pin P4.6/XI/SCS_ (RTC/CLK)
10P4.7/XO/SCK_I/OMultiplexed I/O & Peripheral Pin P4.7/XO/SCK_ (SPI, RTC/CLK)
11P2.5/TNOW/T2EX_/CAP2_I/OMultiplexed I/O & Peripheral Pin P2.5/TNOW/T2EX_/CAP2_ (General)
12P2.6/RXD1I/OMultiplexed I/O & Peripheral Pin P2.6/RXD1 (UART)
13P2.7/TXD1I/OMultiplexed I/O & Peripheral Pin P2.7/TXD1 (UART)
14P5.1/DPI/OMultiplexed I/O & Peripheral Pin P5.1/DP (General)
15P5.0/DMI/OMultiplexed I/O & Peripheral Pin P5.0/DM (General)
16P0.3/TXD_I/OMultiplexed I/O & Peripheral Pin P0.3/TXD_ (UART)
17P0.2/RXD_I/OMultiplexed I/O & Peripheral Pin P0.2/RXD_ (UART)
18GND/VSSGNDGround Reference Pin (GND/VSS)
19VIN5PowerPower Supply Input (VIN5 — 3.3V / 5.0V Standard Logic)
20VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
PIN 1 P5 1 .
I/O
Multiplexed I/O & Peripheral Pin P5 1 . (General)
Design note: Signal terminal P5 1 . (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5 1 .. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH558T (WCH · SSOP-20-208mil)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH558T (SSOP-20-208mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH558T (SSOP-20-208mil) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH558T (SSOP-20-208mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH558T (SSOP-20-208mil) - 4. Package Dimensions (D×E×A)
SSOP-20-208mil · 5.30×7.20mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH558T (SSOP-20-208mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH558T (SSOP-20-208mil) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH558
P1 · p01_fig011745×916px
CH558T (SSOP-20-208mil) — CH558 内置了ADC 模数转换、4 组定时器和PWM、双异步串口、SPI、USB 设备控制器和全速收发 器等功能模块。
CH558 内置了ADC 模数转换、4 组定时器和PWM、双异步串口、SPI、USB 设备控制器和全速收发 器等功能模块。
P2 · p02_fig011752×1371px
CH558T (SSOP-20-208mil) — 电源输入。支持低功耗睡眠，支持USB、UART0、UART1、SPI0 以及部分GPIO 外部唤醒。 l 芯片内置唯一ID 号，支持ID 号和校验。
电源输入。支持低功耗睡眠，支持USB、UART0、UART1、SPI0 以及部分GPIO 外部唤醒。 l 芯片内置唯一ID 号，支持ID 号和校验。
P2 · p02_fig01P2
CH558T (SSOP-20-208mil) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P46 · p46_fig011757×2656px
CH558T (SSOP-20-208mil) — CH558 手册 46 | 为1 则转为TNOW 输出，输出正在发送的状态，可以用于 控制RS485 等半双工模式的收发切换 | 5 bMCR_AUTO_FLOW RW | 0 | 4 bMCR_LOOP RW | 内部回路的测试模式使能位，该位为0 禁止内部回路测 试；该位为1 使能内部回路测试。 在内部回路的测试模式下，串口所有对外输出引脚均为无 效状态，TXD1 内部返回到RXD1，RTS 内部返回到CTS，DTR 内部返回到DSR，OUT1 内部返回到RI，OUT2
CH558 手册 46 | 为1 则转为TNOW 输出，输出正在发送的状态，可以用于 控制RS485 等半双工模式的收发切换 | 5 bMCR_AUTO_FLOW RW | 0 | 4 bMCR_LOOP RW | 内部回路的测试模式使能位，该位为0 禁止内部回路测 试；该位为1 使能内部回路测试。 在内部回路的测试模式下，串口所有对外输出引脚均为无 效状态，TXD1 内部返回到RXD1，RTS 内部返回到CTS，DTR 内部返回到DSR，OUT1 内部返回到RI，OUT2
P47 · p47_fig011757×1008px
CH558T (SSOP-20-208mil) — CH558 手册 47 | 调制解调器MODEM 状态寄存器(SER1_MSR)： | 位 名称 访问 描述 复位值 | 7 bMSR_DCD R0 该位是DCD 引脚的位反，为1 表示DCD 引脚有效(低电平有效) 1 | 6 bMSR_RI R0 该位是RI 引脚的位反，为1 表示RI 引脚有效(低电平有效) 1 | 5 bMSR_DSR R0 该位是DSR 引脚的位反，为1 表示DSR 引脚有效(低电平有效) 1 | 4 bMSR_CTS R0 该位是CTS 引脚的位反
CH558 手册 47 | 调制解调器MODEM 状态寄存器(SER1_MSR)： | 位 名称 访问 描述 复位值 | 7 bMSR_DCD R0 该位是DCD 引脚的位反，为1 表示DCD 引脚有效(低电平有效) 1 | 6 bMSR_RI R0 该位是RI 引脚的位反，为1 表示RI 引脚有效(低电平有效) 1 | 5 bMSR_DSR R0 该位是DSR 引脚的位反，为1 表示DSR 引脚有效(低电平有效) 1 | 4 bMSR_CTS R0 该位是CTS 引脚的位反
P47 · p47_fig021757×734px
CH558T (SSOP-20-208mil) — 位 名称 访问 描述 复位值 | [7:0] SER1_DLL RW SER1_DLL 是低字节，SER1_DLM 是高字节，两者组成16 位除数，用于由16 位计数器构成的串口波特率产生器。 只有当bLCR_DLAB 为1 时，才能读写这两个寄存器。 该除数 = Fsys * 2 / SER1_DIV / 16 / 波特率 | xxh | [7:0] SER1_DLM RW 80h | UART1 预分频除数寄存器(SER1_DIV)，仅当bLCR_DLAB=1 时有效：
位 名称 访问 描述 复位值 | [7:0] SER1_DLL RW SER1_DLL 是低字节，SER1_DLM 是高字节，两者组成16 位除数，用于由16 位计数器构成的串口波特率产生器。 只有当bLCR_DLAB 为1 时，才能读写这两个寄存器。 该除数 = Fsys * 2 / SER1_DIV / 16 / 波特率 | xxh | [7:0] SER1_DLM RW 80h | UART1 预分频除数寄存器(SER1_DIV)，仅当bLCR_DLAB=1 时有效：

Technical Specifications & Part Details (CH558T)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH558T (SSOP-20-208mil) is a 20-pin standard electronic & interconnect component featuring a 7.20 × 5.30 × 1.85 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
12MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.20 × 5.30 × 1.85 mm (A1=0.15 mm)
Package family: TSSOP (SSOP-20-208mil)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SSOP-20-208mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.20 × 5.30 mm
Height (A) & Pitch (e)IPC-7351B
A=1.85mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.60 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SSOP-20-208mil
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH558T (SSOP-20-208mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH558T (SSOP-20-208mil)?

Manufactured by WCH, the CH558T is housed in a SSOP-20-208mil package with 20 pins and a 0.65 mm lead pitch. Key pins include: 1 (P5 1 .: Multiplexed I/O & Peripheral Pin P5 1 . (General)), 2 (bP4_DRV: Multiplexed I/O & Peripheral Pin bP4_DRV (General)), 3 (bSPI0_PINX_: Multiplexed I/O & Peripheral Pin bSPI0_PINX_ (General)), 4 (P5 4 .: Multiplexed I/O & Peripheral Pin P5 4 . (General)), 5 (P1.7/AIN7/SCK: Multiplexed I/O & Peripheral Pin P1.7/AIN7/SCK (SPI, ADC)), 6 (P5.7/RST: Multiplexed I/O & Peripheral Pin P5.7/RST (General)).

What are the IPC-7351B PCB Footprint dimensions for CH558T?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH558T (SSOP-20-208mil) has a nominal body envelope of 5.30 × 7.20 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH558T?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH558T (WCH, SSOP-20-208mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & CH558 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1P5 1 .Digital_IOSignal terminal P5 1 . (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5 1 .. Supported peripheral buses: General.
2bP4_DRVDigital_IOSignal terminal bP4_DRV (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: bP4_DRV. Supported peripheral buses: General.
3bSPI0_PINX_Digital_IOSignal terminal bSPI0_PINX_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: bSPI0_PINX_. Supported peripheral buses: General.
4P5 4 .Digital_IOSignal terminal P5 4 . (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5 4 .. Supported peripheral buses: General.
5P1.7/AIN7/SCKDigital_IOSignal terminal P1.7/AIN7/SCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI, ADC.
6P5.7/RSTDigital_IOSignal terminal P5.7/RST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.7/RST. Supported peripheral buses: General.
7P3.2/LED0/INT0Digital_IOSignal terminal P3.2/LED0/INT0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.2/LED0/INT0. Supported peripheral buses: General.
8P3.4/LEDC/T0Digital_IOSignal terminal P3.4/LEDC/T0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.4/LEDC/T0. Supported peripheral buses: General.
9P4.6/XI/SCS_Digital_IOSignal terminal P4.6/XI/SCS_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.6/XI/SCS_. Supported peripheral buses: RTC/CLK.
10P4.7/XO/SCK_Digital_IOSignal terminal P4.7/XO/SCK_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI, RTC/CLK.
11P2.5/TNOW/T2EX_/CAP2_Digital_IOSignal terminal P2.5/TNOW/T2EX_/CAP2_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.5/TNOW/T2EX_/CAP2_. Supported peripheral buses: General.
12P2.6/RXD1Digital_IOSignal terminal P2.6/RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.6/RXD1. Supported peripheral buses: UART.
13P2.7/TXD1Digital_IOSignal terminal P2.7/TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.7/TXD1. Supported peripheral buses: UART.
14P5.1/DPDigital_IOSignal terminal P5.1/DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.1/DP. Supported peripheral buses: General.
15P5.0/DMDigital_IOSignal terminal P5.0/DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.0/DM. Supported peripheral buses: General.
16P0.3/TXD_Digital_IOSignal terminal P0.3/TXD_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.3/TXD_. Supported peripheral buses: UART.
17P0.2/RXD_Digital_IOSignal terminal P0.2/RXD_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.2/RXD_. Supported peripheral buses: UART.
18GND/VSSGND0V electrical ground return terminal (GND/VSS) for internal core logic, I/O drivers, and analog sub-blocks.
19VIN5Power_InPrimary positive power supply input (VIN5) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
20VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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