25C080-E/P (PDIP-8) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of 25C080-E/P (PDIP-8)?

Manufactured by MICROCHIP, the 25C080-E/P is housed in a PDIP-8 package with 8 pins and a 2.54 mm lead pitch, supporting a VCC supply range of 1.8V to 5.5V. Key pins include: 1 (CS: Multiplexed I/O & Peripheral Pin CS (General)), 2 (SO: Multiplexed I/O & Peripheral Pin SO (General)), 3 (WP: Multiplexed I/O & Peripheral Pin WP (General)), 4 (Vss: Ground Reference Pin (Vss)), 5 (SI: Multiplexed I/O & Peripheral Pin SI (General)), 6 (SCK: Multiplexed I/O & Peripheral Pin SCK (SPI)).

Q: What are the IPC-7351B PCB Footprint dimensions for 25C080-E/P?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), 25C080-E/P (PDIP-8) has a nominal body envelope of 6.35 × 9.62 mm, pitch e = 2.54 mm, and 8 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for 25C080-E/P?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for 25C080-E/P (MICROCHIP, PDIP-8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 6.35mm × 9.62mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (8/8)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	CS	I/O	Multiplexed I/O & Peripheral Pin CS (General)
2	SO	I/O	Multiplexed I/O & Peripheral Pin SO (General)
3	WP	I/O	Multiplexed I/O & Peripheral Pin WP (General)
4	Vss	GND	Ground Reference Pin (Vss)
5	SI	I/O	Multiplexed I/O & Peripheral Pin SI (General)
6	SCK	I/O	Multiplexed I/O & Peripheral Pin SCK (SPI)
7	HOLD	I/O	Multiplexed I/O & Peripheral Pin HOLD (General)
8	Vcc	Power	Power Supply Input (Vcc — 1.8V to 5.5V)

PIN 1 CS

I/O

Multiplexed I/O & Peripheral Pin CS (General)

Design note: ChipSelectInput

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

25C080-E/P (PDIP-8) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

25C080-E/P (PDIP-8) - 2. Standard Pinout (Top View)

True package pinout (8 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

25C080-E/P (PDIP-8) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

25C080-E/P (PDIP-8) - 4. Package Dimensions (D×E×A)

PDIP-8 · 6.35×9.62mm · Pitch 2.54mmExpand ›

5. Recommended Land PatternLAND PATTERN

25C080-E/P (PDIP-8) - 5. Recommended Land Pattern

IPC-7351B Footprint (8 Pads)Expand ›

6. Application SchematicSCHEMATIC

25C080-E/P (PDIP-8) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)

Showing 1–11 of 11 uncropped original figures for 25C080

P13 · p13_fig01EXACT PACKAGE

25AA080/25LC080/25C080

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25LC080 2.5-5.5V 2 MHz I

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Please use 25AA080A/B or 25LC080A/B.

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P1 · p01_fig02P1

Datasheet Page 1 (p01_fig02)

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25C080-E/P (PDIP-8) — Legend: XX...X Customer specific information* Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code | Note: In the event the

Legend: XX...X Customer specific information* Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code | Note: In the event the

P13 · p13_fig01P13

Datasheet Page 13 (p13_fig01)

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25C080-E/P (PDIP-8) — B1 | B | A1 | A | L | A2 | p |  | E | eB |  | c | E1 | n | D | 1 | 2 | Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

B1 | B | A1 | A | L | A2 | p |  | E | eB |  | c | E1 | n | D | 1 | 2 | Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

P14 · p14_fig021442×1187px

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25C080-E/P (PDIP-8) — Foot Angle f 0 4 8 0 4 8 | 15 12 0 15 12 0  Mold Draft Angle Bottom | 15 12 0 15 12 0  Mold Draft Angle Top | 0.51 0.42 0.33 .020 .017 .013 B Lead Width | 0.25 0.23 0.20 .010 .009 .008 c Lead Thickness | 0.76 0.62 0.48 .030 .025 .019 L Fo

P1 · p01_fig03All Packages in PDF

EEPROM

Technical Specifications & Part Details (25C080-E/P)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:25C080-E/P (PDIP-8) is a 8-pin standard electronic & interconnect component featuring a 9.62 × 6.35 × 4.20 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 1.8V to 5.5V supply operation across -40°C to +125°C with integrated SPI interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V to 5.5V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to +125°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

1 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

9.62 × 6.35 × 4.20 mm (A1=0.51 mm)

Package family: DIP (PDIP-8)

Pin Count & Lead PitchN / e

8 Pins | Pitch e = 2.54 mm (100.0 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

SPI

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol8 auto-grouped pins

IPC-7351B Land Pattern8 pads · Pitch 2.54mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PDIP-8)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

9.62 × 6.35 mm

Height (A) & Pitch (e)IPC-7351B

A=4.20mm · e=2.54mm

Pad Size (W × L)Level B

1.60 × 1.60 mm

Pins / Total PadsTopology

8P / 8Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit PDIP-8	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — 25C080-E/P (PDIP-8)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of 25C080-E/P (PDIP-8)?

Manufactured by MICROCHIP, the 25C080-E/P is housed in a PDIP-8 package with 8 pins and a 2.54 mm lead pitch, supporting a VCC supply range of 1.8V to 5.5V. Key pins include: 1 (CS: Multiplexed I/O & Peripheral Pin CS (General)), 2 (SO: Multiplexed I/O & Peripheral Pin SO (General)), 3 (WP: Multiplexed I/O & Peripheral Pin WP (General)), 4 (Vss: Ground Reference Pin (Vss)), 5 (SI: Multiplexed I/O & Peripheral Pin SI (General)), 6 (SCK: Multiplexed I/O & Peripheral Pin SCK (SPI)).

What are the IPC-7351B PCB Footprint dimensions for 25C080-E/P?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), 25C080-E/P (PDIP-8) has a nominal body envelope of 6.35 × 9.62 mm, pitch e = 2.54 mm, and 8 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for 25C080-E/P?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for 25C080-E/P (MICROCHIP, PDIP-8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (8 pins) & 25C080 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	CS	Digital_IO	Signal terminal CS (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: CS. Supported peripheral buses: General.
2	SO	Digital_IO	Signal terminal SO (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: SO. Supported peripheral buses: General.
3	WP	Digital_IO	Signal terminal WP (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: WP. Supported peripheral buses: General.
4	Vss	GND	0V electrical ground return terminal (Vss) for internal core logic, I/O drivers, and analog sub-blocks.
5	SI	Digital_IO	Signal terminal SI (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: SI. Supported peripheral buses: General.
6	SCK	Digital_IO	Signal terminal SCK (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: SCK. Supported peripheral buses: SPI.
7	HOLD	Digital_IO	Signal terminal HOLD (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: HOLD. Supported peripheral buses: General.
8	Vcc	Power_In	Primary positive power supply input (Vcc) operating in the 1.8V to 5.5V domain (Max rating: 5.5V).

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