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CH343P (TQFN-16-EP(3x3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH343P

WCHID: C2846043TQFN-16-EP(3x3) · 17 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH343P (TQFN-16-EP(3x3))1VIO2GND3VDD54TXD5RXD6V37UD+8UD -9VBUS17EP16RI15CTS14DSR13RTS12DTR TNOW11DCD10ACT#Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.217.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617E=3.00mm · Pitch e=0.50mmD=3.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.00mm × 3.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (17/17)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VIOI/OMultiplexed I/O & Peripheral Pin VIO (General)
2GNDGNDGround Reference Pin (GND)
3VDD5PowerPower Supply Input (VDD5 — 3.3V to 5V)
4TXDI/OMultiplexed I/O & Peripheral Pin TXD (UART)
5RXDI/OMultiplexed I/O & Peripheral Pin RXD (UART)
6V3PowerRegulated Power Output (V3 — 3.3V to 5V)
7UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
8UD -I/OMultiplexed I/O & Peripheral Pin UD - (USB)
9VBUSPowerPower Supply Input (VBUS — 3.3V to 5V)
10ACT#I/OMultiplexed I/O & Peripheral Pin ACT# (USB)
11DCDI/OMultiplexed I/O & Peripheral Pin DCD (UART)
12DTR TNOWI/OMultiplexed I/O & Peripheral Pin DTR TNOW (UART)
13RTSI/OMultiplexed I/O & Peripheral Pin RTS (UART)
14DSRI/OMultiplexed I/O & Peripheral Pin DSR (UART)
15CTSI/OMultiplexed I/O & Peripheral Pin CTS (UART)
16RII/OMultiplexed I/O & Peripheral Pin RI (UART)
17EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 VIO
I/O
Multiplexed I/O & Peripheral Pin VIO (General)
Design note: I/O端口电源输入端 需要外接退耦电容 ，
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH343P (WCH · TQFN-16-EP(3x3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH343P (TQFN-16-EP(3x3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH343P (TQFN-16-EP(3x3)) - 2. Standard Pinout (Top View)
True package pinout (17 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH343P (TQFN-16-EP(3x3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH343P (TQFN-16-EP(3x3)) - 4. Package Dimensions (D×E×A)
TQFN-16-EP(3x3) · 3.00×3.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH343P (TQFN-16-EP(3x3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (17 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH343P (TQFN-16-EP(3x3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CH343
P1 · p01_fig011463×441px
CH343P (TQFN-16-EP(3x3)) — 2、特点
2、特点
P1 · p01_fig021745×489px
CH343P (TQFN-16-EP(3x3)) — 3、封装
3、封装
P1 · p01_fig02P1
CH343P (TQFN-16-EP(3x3)) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P5 · p05_fig011706×1764px
CH343P (TQFN-16-EP(3x3)) — 6.1. 绝对最大值（临界或者超过绝对最大值将可能导致芯片工作不正常甚至损坏）
6.1. 绝对最大值（临界或者超过绝对最大值将可能导致芯片工作不正常甚至损坏）
P7 · p07_fig01899×662px
CH343P (TQFN-16-EP(3x3)) — 7.3. USB 转RS485（下图）
7.3. USB 转RS485（下图）
P7 · p07_fig02601×261px
CH343P (TQFN-16-EP(3x3)) — 图中DTR 引脚外接下拉电阻，从而切换为TNOW 引脚，用于控制RS485 收发器的DE（高有效发送 使能）和RE#（低有效接收使能）引脚。RS485 收发器应该与VIO 使用同一供电电源。
图中DTR 引脚外接下拉电阻，从而切换为TNOW 引脚，用于控制RS485 收发器的DE（高有效发送 使能）和RE#（低有效接收使能）引脚。RS485 收发器应该与VIO 使用同一供电电源。
P7 · p07_fig03662×338px
CH343P (TQFN-16-EP(3x3)) — 上图是双供电方式下MCU 单片机通过TTL 串口连接CH343 芯片实现USB 通讯的参考电路。CH343 由USB 总线供电VBUS，MCU 及VIO 使用另一自供电源VDD，VDD 支持5V、3.3V、2.5V、1.8V。CH343 与MCU 连接时可以免除二极管等防倒灌电路。
上图是双供电方式下MCU 单片机通过TTL 串口连接CH343 芯片实现USB 通讯的参考电路。CH343 由USB 总线供电VBUS，MCU 及VIO 使用另一自供电源VDD，VDD 支持5V、3.3V、2.5V、1.8V。CH343 与MCU 连接时可以免除二极管等防倒灌电路。
P7 · p07_fig03P7
CH343P (TQFN-16-EP(3x3)) — Datasheet Page 7 (p07_fig03)
Datasheet Page 7 (p07_fig03)
P8 · p08_fig011399×786px
CH343P (TQFN-16-EP(3x3)) — 设置OUT1 有效，则VBUS 的下拉电阻关闭，从而使PMOS 的栅极失去电压而关闭，最终VIO 电压降低 导致MCU 低压复位。当VIO 电压下降到约1.4V 左右时，触发VIO 低压保护机制，VBUS 自动吸收下拉 电流并恢复下拉电阻，使得PMOS 重新开启，VIO 恢复供电。整个过程实现了VIO 降压和MCU 复位。 发光管D1 用于避免VBUS 电压太低，另外，在Q1 与VDD 之间串联二极管可以防止VDD 向+5 倒灌。
设置OUT1 有效，则VBUS 的下拉电阻关闭，从而使PMOS 的栅极失去电压而关闭，最终VIO 电压降低 导致MCU 低压复位。当VIO 电压下降到约1.4V 左右时，触发VIO 低压保护机制，VBUS 自动吸收下拉 电流并恢复下拉电阻，使得PMOS 重新开启，VIO 恢复供电。整个过程实现了VIO 降压和MCU 复位。 发光管D1 用于避免VBUS 电压太低，另外，在Q1 与VDD 之间串联二极管可以防止VDD 向+5 倒灌。

Technical Specifications & Part Details (CH343P)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH343P (TQFN-16-EP(3x3)) is a 16-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.3V to 5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.3V to 5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (TQFN-16-EP(3x3))
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol17 auto-grouped pins
OK
IPC-7351B Land Pattern17 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 1.70×1.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TQFN-16-EP(3x3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.75 mm
Pins / Total PadsTopology
17P / 17Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TQFN-16-EP(3x3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH343P (TQFN-16-EP(3x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH343P (TQFN-16-EP(3x3))?

Manufactured by WCH, the CH343P is housed in a TQFN-16-EP(3x3) package with 17 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 3.3V to 5V. Key pins include: 1 (VIO: Multiplexed I/O & Peripheral Pin VIO (General)), 2 (GND: Ground Reference Pin (GND)), 3 (VDD5: Power Supply Input (VDD5 — 3.3V to 5V)), 4 (TXD: Multiplexed I/O & Peripheral Pin TXD (UART)), 5 (RXD: Multiplexed I/O & Peripheral Pin RXD (UART)), 6 (V3: Regulated Power Output (V3 — 3.3V to 5V)).

What are the IPC-7351B PCB Footprint dimensions for CH343P?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH343P (TQFN-16-EP(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 17 copper pads plus a central exposed thermal pad (EPAD) of 1.70 × 1.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH343P?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH343P (WCH, TQFN-16-EP(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (17 pins) & CH343 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VIODigital_IOSignal terminal VIO (I/O, 3.3V to 5V domain). Multiplexed alternate functions: VIO. Supported peripheral buses: General.
2GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
3VDD5Power_InPrimary positive power supply input (VDD5) operating in the 3.3V to 5V domain (Max rating: 5.0V).
4TXDDigital_IOSignal terminal TXD (I/O, 3.3V to 5V domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
5RXDDigital_IOSignal terminal RXD (I/O, 3.3V to 5V domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART.
6V3Power_OutRegulated power output rail (V3) operating in the 3.3V to 5V domain (Max rating: 5.0V).
7UD+Digital_IOSignal terminal UD+ (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
8UD -Digital_IOSignal terminal UD - (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD -. Supported peripheral buses: USB.
9VBUSPower_InPrimary positive power supply input (VBUS) operating in the 3.3V to 5V domain (Max rating: 5.0V).
10ACT#Digital_IOSignal terminal ACT# (I/O, 3.3V to 5V domain). Multiplexed alternate functions: ACT#. Supported peripheral buses: USB.
11DCDDigital_IOSignal terminal DCD (I/O, 3.3V to 5V domain). Multiplexed alternate functions: DCD. Supported peripheral buses: UART.
12DTR TNOWDigital_IOSignal terminal DTR TNOW (I/O, 3.3V to 5V domain). Multiplexed alternate functions: DTR TNOW. Supported peripheral buses: UART.
13RTSDigital_IOSignal terminal RTS (I/O, 3.3V to 5V domain). Multiplexed alternate functions: RTS. Supported peripheral buses: UART.
14DSRDigital_IOSignal terminal DSR (I/O, 3.3V to 5V domain). Multiplexed alternate functions: DSR. Supported peripheral buses: UART.
15CTSDigital_IOSignal terminal CTS (I/O, 3.3V to 5V domain). Multiplexed alternate functions: CTS. Supported peripheral buses: UART.
16RIDigital_IOSignal terminal RI (I/O, 3.3V to 5V domain). Multiplexed alternate functions: RI. Supported peripheral buses: UART.
17EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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